; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s

; i256 shift left with variable amount
define i256 @shl_i256(i256 %a, i256 %amt) nounwind {
; CHECK-LABEL: shl_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #64
; CHECK-NEXT:    movi v0.2d, #0000000000000000
; CHECK-NEXT:    lsr x8, x4, #3
; CHECK-NEXT:    mov x9, sp
; CHECK-NEXT:    add x9, x9, #32
; CHECK-NEXT:    stp x2, x3, [sp, #48]
; CHECK-NEXT:    mvn w14, w4
; CHECK-NEXT:    and x8, x8, #0x18
; CHECK-NEXT:    stp x0, x1, [sp, #32]
; CHECK-NEXT:    and x11, x4, #0x3f
; CHECK-NEXT:    sub x8, x9, x8
; CHECK-NEXT:    eor x11, x11, #0x3f
; CHECK-NEXT:    stp q0, q0, [sp]
; CHECK-NEXT:    ldp x10, x9, [x8]
; CHECK-NEXT:    ldp x12, x8, [x8, #16]
; CHECK-NEXT:    lsr x13, x9, #1
; CHECK-NEXT:    lsr x15, x10, #1
; CHECK-NEXT:    lsl x9, x9, x4
; CHECK-NEXT:    lsl x8, x8, x4
; CHECK-NEXT:    lsl x0, x10, x4
; CHECK-NEXT:    lsr x13, x13, x14
; CHECK-NEXT:    lsr x14, x12, #1
; CHECK-NEXT:    lsr x15, x15, x11
; CHECK-NEXT:    lsl x12, x12, x4
; CHECK-NEXT:    lsr x11, x14, x11
; CHECK-NEXT:    orr x1, x9, x15
; CHECK-NEXT:    orr x2, x12, x13
; CHECK-NEXT:    orr x3, x8, x11
; CHECK-NEXT:    add sp, sp, #64
; CHECK-NEXT:    ret
  %r = shl i256 %a, %amt
  ret i256 %r
}

; i256 logical shift right with variable amount
define i256 @lshr_i256(i256 %a, i256 %amt) nounwind {
; CHECK-LABEL: lshr_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #64
; CHECK-NEXT:    movi v0.2d, #0000000000000000
; CHECK-NEXT:    lsr x8, x4, #3
; CHECK-NEXT:    mov x9, sp
; CHECK-NEXT:    stp x2, x3, [sp, #16]
; CHECK-NEXT:    and x11, x4, #0x3f
; CHECK-NEXT:    mvn w13, w4
; CHECK-NEXT:    and x8, x8, #0x18
; CHECK-NEXT:    stp x0, x1, [sp]
; CHECK-NEXT:    eor x11, x11, #0x3f
; CHECK-NEXT:    add x8, x9, x8
; CHECK-NEXT:    stp q0, q0, [sp, #32]
; CHECK-NEXT:    ldp x9, x10, [x8]
; CHECK-NEXT:    ldp x12, x8, [x8, #16]
; CHECK-NEXT:    lsl x14, x10, #1
; CHECK-NEXT:    lsr x9, x9, x4
; CHECK-NEXT:    lsr x10, x10, x4
; CHECK-NEXT:    lsl x15, x12, #1
; CHECK-NEXT:    lsl x16, x8, #1
; CHECK-NEXT:    lsr x12, x12, x4
; CHECK-NEXT:    lsl x14, x14, x11
; CHECK-NEXT:    lsr x3, x8, x4
; CHECK-NEXT:    lsl x8, x15, x13
; CHECK-NEXT:    lsl x11, x16, x11
; CHECK-NEXT:    orr x0, x14, x9
; CHECK-NEXT:    orr x1, x10, x8
; CHECK-NEXT:    orr x2, x11, x12
; CHECK-NEXT:    add sp, sp, #64
; CHECK-NEXT:    ret
  %r = lshr i256 %a, %amt
  ret i256 %r
}

; i256 arithmetic shift right with variable amount
define i256 @ashr_i256(i256 %a, i256 %amt) nounwind {
; CHECK-LABEL: ashr_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #64
; CHECK-NEXT:    lsr x9, x4, #3
; CHECK-NEXT:    asr x8, x3, #63
; CHECK-NEXT:    mov x10, sp
; CHECK-NEXT:    stp x2, x3, [sp, #16]
; CHECK-NEXT:    mvn w14, w4
; CHECK-NEXT:    and x13, x4, #0x3f
; CHECK-NEXT:    and x9, x9, #0x18
; CHECK-NEXT:    stp x0, x1, [sp]
; CHECK-NEXT:    eor x13, x13, #0x3f
; CHECK-NEXT:    stp x8, x8, [sp, #48]
; CHECK-NEXT:    add x9, x10, x9
; CHECK-NEXT:    stp x8, x8, [sp, #32]
; CHECK-NEXT:    ldp x10, x8, [x9, #8]
; CHECK-NEXT:    ldr x11, [x9]
; CHECK-NEXT:    ldr x9, [x9, #24]
; CHECK-NEXT:    lsr x11, x11, x4
; CHECK-NEXT:    lsl x12, x8, #1
; CHECK-NEXT:    lsl x15, x10, #1
; CHECK-NEXT:    lsr x10, x10, x4
; CHECK-NEXT:    lsr x8, x8, x4
; CHECK-NEXT:    asr x3, x9, x4
; CHECK-NEXT:    lsl x12, x12, x14
; CHECK-NEXT:    lsl x14, x9, #1
; CHECK-NEXT:    lsl x15, x15, x13
; CHECK-NEXT:    lsl x13, x14, x13
; CHECK-NEXT:    orr x0, x15, x11
; CHECK-NEXT:    orr x1, x10, x12
; CHECK-NEXT:    orr x2, x13, x8
; CHECK-NEXT:    add sp, sp, #64
; CHECK-NEXT:    ret
  %r = ashr i256 %a, %amt
  ret i256 %r
}

; i256 shift left by constant
define i256 @shl_i256_const(i256 %a) nounwind {
; CHECK-LABEL: shl_i256_const:
; CHECK:       // %bb.0:
; CHECK-NEXT:    extr x8, x2, x1, #47
; CHECK-NEXT:    lsl x9, x0, #17
; CHECK-NEXT:    extr x1, x1, x0, #47
; CHECK-NEXT:    extr x3, x3, x2, #47
; CHECK-NEXT:    mov x0, x9
; CHECK-NEXT:    mov x2, x8
; CHECK-NEXT:    ret
  %r = shl i256 %a, 17
  ret i256 %r
}

; i256 logical shift right by constant
define i256 @lshr_i256_const(i256 %a) nounwind {
; CHECK-LABEL: lshr_i256_const:
; CHECK:       // %bb.0:
; CHECK-NEXT:    extr x0, x1, x0, #17
; CHECK-NEXT:    extr x1, x2, x1, #17
; CHECK-NEXT:    extr x2, x3, x2, #17
; CHECK-NEXT:    lsr x3, x3, #17
; CHECK-NEXT:    ret
  %r = lshr i256 %a, 17
  ret i256 %r
}

; i256 arithmetic shift right by constant
define i256 @ashr_i256_const(i256 %a) nounwind {
; CHECK-LABEL: ashr_i256_const:
; CHECK:       // %bb.0:
; CHECK-NEXT:    extr x0, x1, x0, #17
; CHECK-NEXT:    extr x1, x2, x1, #17
; CHECK-NEXT:    extr x2, x3, x2, #17
; CHECK-NEXT:    asr x3, x3, #17
; CHECK-NEXT:    ret
  %r = ashr i256 %a, 17
  ret i256 %r
}