; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; FIXME: Enable for VI. declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { ; GCN-LABEL: test_div_fmas_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; GCN-NEXT: s_load_dword s6, s[4:5], 0x13 ; GCN-NEXT: s_load_dword s2, s[4:5], 0x2e ; GCN-NEXT: s_load_dword s7, s[4:5], 0x1c ; GCN-NEXT: s_load_dword s4, s[4:5], 0x25 ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { ; GCN-LABEL: test_div_fmas_f32_inline_imm_0: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; GCN-NEXT: s_load_dword s2, s[4:5], 0x2e ; GCN-NEXT: s_load_dword s6, s[4:5], 0x1c ; GCN-NEXT: s_load_dword s4, s[4:5], 0x25 ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s4 ; GCN-NEXT: v_div_fmas_f32 v0, 1.0, v0, v1 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm %result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, float %a, float %b, float %c, [8 x i32], i1 %d) nounwind { ; GCN-LABEL: test_div_fmas_f32_inline_imm_1: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; GCN-NEXT: s_load_dword s2, s[4:5], 0x16 ; GCN-NEXT: s_load_dword s6, s[4:5], 0xb ; GCN-NEXT: s_load_dword s4, s[4:5], 0xd ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s4 ; GCN-NEXT: v_div_fmas_f32 v0, v0, 1.0, v1 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { ; GCN-LABEL: test_div_fmas_f32_inline_imm_2: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; GCN-NEXT: s_load_dword s2, s[4:5], 0x2e ; GCN-NEXT: s_load_dword s6, s[4:5], 0x13 ; GCN-NEXT: s_load_dword s4, s[4:5], 0x1c ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s4 ; GCN-NEXT: v_div_fmas_f32 v0, v0, v1, 1.0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, double %b, double %c, i1 %d) nounwind { ; GCN-LABEL: test_div_fmas_f64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dword s8, s[4:5], 0x11 ; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0 ; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_mov_b32 s8, s0 ; GCN-NEXT: s_mov_b32 s9, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v1, s3 ; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v3, s5 ; GCN-NEXT: v_mov_b32_e32 v4, s6 ; GCN-NEXT: v_mov_b32_e32 v5, s7 ; GCN-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5] ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: s_endpgm %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone store double %result, ptr addrspace(1) %out, align 8 ret void } define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, float %a, float %b, float %c, i32 %i) nounwind { ; GCN-LABEL: test_div_fmas_f32_cond_to_vcc: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s3, 0 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm %cmp = icmp eq i32 %i, 0 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_imm_false_cond_to_vcc(ptr addrspace(1) %out, float %a, float %b, float %c) nounwind { ; GCN-LABEL: test_div_fmas_f32_imm_false_cond_to_vcc: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: s_mov_b64 vcc, 0 ; GCN-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace(1) %out, float %a, float %b, float %c) nounwind { ; GCN-LABEL: test_div_fmas_f32_imm_true_cond_to_vcc: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: s_mov_b64 vcc, -1 ; GCN-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone store float %result, ptr addrspace(1) %out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %d) nounwind { ; GCN-LABEL: test_div_fmas_f32_logical_cond_to_vcc: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; GCN-NEXT: s_load_dword s8, s[4:5], 0xd ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, 0 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b64 s[4:5], s[2:3] ; GCN-NEXT: buffer_load_dword v0, v[1:2], s[4:7], 0 addr64 glc ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_load_dword v3, v[1:2], s[4:7], 0 addr64 offset:4 glc ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_load_dword v1, v[1:2], s[4:7], 0 addr64 offset:8 glc ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_cmp_lg_u32 s8, 0 ; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0 ; GCN-NEXT: s_and_b64 vcc, vcc, s[2:3] ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s3, s7 ; GCN-NEXT: v_div_fmas_f32 v0, v0, v3, v1 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8 ; GCN-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.a = getelementptr float, ptr addrspace(1) %in, i32 %tid %gep.b = getelementptr float, ptr addrspace(1) %gep.a, i32 1 %gep.c = getelementptr float, ptr addrspace(1) %gep.a, i32 2 %gep.out = getelementptr float, ptr addrspace(1) %out, i32 2 %a = load volatile float, ptr addrspace(1) %gep.a %b = load volatile float, ptr addrspace(1) %gep.b %c = load volatile float, ptr addrspace(1) %gep.c %cmp0 = icmp eq i32 %tid, 0 %cmp1 = icmp ne i32 %d, 0 %and = and i1 %cmp0, %cmp1 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone store float %result, ptr addrspace(1) %gep.out, align 4 ret void } define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(1) %dummy) nounwind { ; GCN-LABEL: test_div_fmas_f32_i1_phi_vcc: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, 0 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0 ; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b64 s[0:1], s[10:11] ; GCN-NEXT: buffer_load_dwordx2 v[1:2], v[3:4], s[0:3], 0 addr64 ; GCN-NEXT: buffer_load_dword v3, v[3:4], s[0:3], 0 addr64 offset:8 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0 ; GCN-NEXT: s_mov_b64 vcc, 0 ; GCN-NEXT: s_and_saveexec_b64 s[10:11], s[0:1] ; GCN-NEXT: s_cbranch_execz .LBB9_2 ; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s7, s3 ; GCN-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GCN-NEXT: s_and_b64 vcc, vcc, exec ; GCN-NEXT: .LBB9_2: ; %exit ; GCN-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_nop 0 ; GCN-NEXT: v_div_fmas_f32 v0, v1, v2, v3 ; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_mov_b32 s11, s3 ; GCN-NEXT: buffer_store_dword v0, off, s[8:11], 0 offset:8 ; GCN-NEXT: s_endpgm entry: %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.out = getelementptr float, ptr addrspace(1) %out, i32 2 %gep.a = getelementptr float, ptr addrspace(1) %in, i32 %tid %gep.b = getelementptr float, ptr addrspace(1) %gep.a, i32 1 %gep.c = getelementptr float, ptr addrspace(1) %gep.a, i32 2 %a = load float, ptr addrspace(1) %gep.a %b = load float, ptr addrspace(1) %gep.b %c = load float, ptr addrspace(1) %gep.c %cmp0 = icmp eq i32 %tid, 0 br i1 %cmp0, label %bb, label %exit bb: %val = load i32, ptr addrspace(1) %dummy %cmp1 = icmp ne i32 %val, 0 br label %exit exit: %cond = phi i1 [false, %entry], [%cmp1, %bb] %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone store float %result, ptr addrspace(1) %gep.out, align 4 ret void } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; SI: {{.*}}