; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6

; RUN: opt -passes=instcombine < %s | llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200  | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
; RUN: opt -passes=instcombine < %s | llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250  | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: opt -passes=instcombine < %s | llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
; RUN: opt -passes=instcombine < %s | llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s

; The address calculation can be simplified and folded because of known bits of mbcnt.
define amdgpu_ps <2 x float> @global_load_scale_add_foldable_knownbits(ptr addrspace(1) inreg %sbase) {
  %v = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
  %mul = shl i32 %v, 1
  %add = add i32 %mul, 32
  %zext.offset = zext i32 %add to i64
  %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset
  %load = load <2 x float>, ptr addrspace(1) %gep
  ret <2 x float> %load
}

; The nsw/nuw helps the folding of address addition.
define amdgpu_ps <2 x float> @global_load_scale_add_foldable_nowrap(ptr addrspace(1) inreg %sbase, i32 %v) {
  %mul = shl nsw nuw i32 %v, 3
  %add = add nsw nuw i32 %mul, 128
  %zext.offset = zext i32 %add to i64
  %gep = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
  %load = load <2 x float>, ptr addrspace(1) %gep
  ret <2 x float> %load
}

; Address calculation cannot be folded because possible overflow during addition.
define amdgpu_ps <2 x float> @global_load_scale_add_unfoldable(ptr addrspace(1) inreg %sbase, i32 %v) {
  %mul = shl i32 %v, 3
  %add = add i32 %mul, 128
  %zext.offset = zext i32 %add to i64
  %gep = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
  %load = load <2 x float>, ptr addrspace(1) %gep
  ret <2 x float> %load
}

declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX12: {{.*}}
; GFX12-GISEL: {{.*}}
; GFX12-SDAG: {{.*}}
; GFX1250: {{.*}}
; GFX1250-GISEL: {{.*}}
; GFX1250-SDAG: {{.*}}