; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s

define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef %dst.coerce, ptr addrspace(1) inreg noundef %src.coerce, i64 inreg noundef %nElts, i64 inreg noundef %redOpArg, i1 inreg noundef %redOpArgIsPtr) #0 !dbg !4 {
; GFX942-LABEL: preload_block_count_x:
; GFX942:       .Lfunc_begin0:
; GFX942-NEXT:    .file 0 "/" "<stdin>"
; GFX942-NEXT:    .cfi_sections .debug_frame
; GFX942-NEXT:    .cfi_startproc
; GFX942-NEXT:  ; %bb.5:
; GFX942-NEXT:    .loc 0 1 0 prologue_end ; <stdin>:1:0
; GFX942-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX942-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x8
; GFX942-NEXT:    s_load_dword s12, s[0:1], 0x28
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    s_branch .LBB0_0
; GFX942-NEXT:    .loc 0 0 0 is_stmt 0 ; :0:0
; GFX942-NEXT:  .Ltmp0:
; GFX942-NEXT:    .p2align 8
; GFX942-NEXT:  ; %bb.6:
; GFX942-NEXT:  .LBB0_0: ; %entry
; GFX942-NEXT:    .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ;
; GFX942-NEXT:    .cfi_undefined 16
; GFX942-NEXT:    s_mov_b32 s0, s13
; GFX942-NEXT:  .Ltmp1:
; GFX942-NEXT:    ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3
; GFX942-NEXT:    .loc 0 1 0 is_stmt 1 ; <stdin>:1
; GFX942-NEXT:    s_ashr_i32 s13, s12, 31
; GFX942-NEXT:    s_or_b64 s[8:9], s[6:7], s[12:13]
; GFX942-NEXT:    s_cmp_lg_u32 s9, 0
; GFX942-NEXT:    s_cbranch_scc0 .LBB0_4
; GFX942-NEXT:  .Ltmp2:
; GFX942-NEXT:  ; %bb.1:
; GFX942-NEXT:    ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3
; GFX942-NEXT:    v_cvt_f32_u32_e32 v0, s12
; GFX942-NEXT:    v_cvt_f32_u32_e32 v1, s13
; GFX942-NEXT:    s_sub_u32 s1, 0, s12
; GFX942-NEXT:    s_subb_u32 s3, 0, s13
; GFX942-NEXT:  .Ltmp3:
; GFX942-NEXT:    v_fmamk_f32 v0, v1, 0x4f800000, v0
; GFX942-NEXT:    v_rcp_f32_e32 v0, v0
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX942-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
; GFX942-NEXT:    v_trunc_f32_e32 v1, v1
; GFX942-NEXT:    v_fmamk_f32 v0, v1, 0xcf800000, v0
; GFX942-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX942-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX942-NEXT:    v_readfirstlane_b32 s5, v1
; GFX942-NEXT:    v_readfirstlane_b32 s10, v0
; GFX942-NEXT:    s_mul_i32 s11, s1, s5
; GFX942-NEXT:    s_mul_hi_u32 s15, s1, s10
; GFX942-NEXT:    s_mul_i32 s14, s3, s10
; GFX942-NEXT:    s_add_i32 s11, s15, s11
; GFX942-NEXT:    s_add_i32 s11, s11, s14
; GFX942-NEXT:    s_mul_i32 s16, s1, s10
; GFX942-NEXT:    s_mul_i32 s15, s10, s11
; GFX942-NEXT:    s_mul_hi_u32 s17, s10, s16
; GFX942-NEXT:    s_mul_hi_u32 s14, s10, s11
; GFX942-NEXT:    s_add_u32 s15, s17, s15
; GFX942-NEXT:    s_addc_u32 s14, 0, s14
; GFX942-NEXT:    s_mul_hi_u32 s18, s5, s16
; GFX942-NEXT:    s_mul_i32 s16, s5, s16
; GFX942-NEXT:    s_add_u32 s15, s15, s16
; GFX942-NEXT:    s_mul_hi_u32 s17, s5, s11
; GFX942-NEXT:    s_addc_u32 s14, s14, s18
; GFX942-NEXT:    s_addc_u32 s15, s17, 0
; GFX942-NEXT:    s_mul_i32 s11, s5, s11
; GFX942-NEXT:    s_add_u32 s11, s14, s11
; GFX942-NEXT:    s_addc_u32 s14, 0, s15
; GFX942-NEXT:    s_add_u32 s10, s10, s11
; GFX942-NEXT:    s_addc_u32 s5, s5, s14
; GFX942-NEXT:    s_mul_i32 s11, s1, s5
; GFX942-NEXT:    s_mul_hi_u32 s14, s1, s10
; GFX942-NEXT:    s_add_i32 s11, s14, s11
; GFX942-NEXT:    s_mul_i32 s3, s3, s10
; GFX942-NEXT:    s_add_i32 s11, s11, s3
; GFX942-NEXT:    s_mul_i32 s1, s1, s10
; GFX942-NEXT:    s_mul_hi_u32 s14, s5, s1
; GFX942-NEXT:    s_mul_i32 s15, s5, s1
; GFX942-NEXT:    s_mul_i32 s17, s10, s11
; GFX942-NEXT:    s_mul_hi_u32 s1, s10, s1
; GFX942-NEXT:    s_mul_hi_u32 s16, s10, s11
; GFX942-NEXT:    s_add_u32 s1, s1, s17
; GFX942-NEXT:    s_addc_u32 s16, 0, s16
; GFX942-NEXT:    s_add_u32 s1, s1, s15
; GFX942-NEXT:    s_mul_hi_u32 s3, s5, s11
; GFX942-NEXT:    s_addc_u32 s1, s16, s14
; GFX942-NEXT:    s_addc_u32 s3, s3, 0
; GFX942-NEXT:    s_mul_i32 s11, s5, s11
; GFX942-NEXT:    s_add_u32 s1, s1, s11
; GFX942-NEXT:    s_addc_u32 s3, 0, s3
; GFX942-NEXT:    s_add_u32 s1, s10, s1
; GFX942-NEXT:    s_addc_u32 s3, s5, s3
; GFX942-NEXT:    s_mul_i32 s10, s6, s3
; GFX942-NEXT:    s_mul_hi_u32 s11, s6, s1
; GFX942-NEXT:    s_mul_hi_u32 s5, s6, s3
; GFX942-NEXT:    s_add_u32 s10, s11, s10
; GFX942-NEXT:    s_addc_u32 s5, 0, s5
; GFX942-NEXT:    s_mul_hi_u32 s14, s7, s1
; GFX942-NEXT:    s_mul_i32 s1, s7, s1
; GFX942-NEXT:    s_add_u32 s1, s10, s1
; GFX942-NEXT:    s_mul_hi_u32 s11, s7, s3
; GFX942-NEXT:    s_addc_u32 s1, s5, s14
; GFX942-NEXT:    s_addc_u32 s5, s11, 0
; GFX942-NEXT:    s_mul_i32 s3, s7, s3
; GFX942-NEXT:    s_add_u32 s1, s1, s3
; GFX942-NEXT:    s_addc_u32 s3, 0, s5
; GFX942-NEXT:    s_mul_i32 s5, s12, s3
; GFX942-NEXT:    s_mul_hi_u32 s10, s12, s1
; GFX942-NEXT:    s_add_i32 s5, s10, s5
; GFX942-NEXT:    s_mul_i32 s10, s13, s1
; GFX942-NEXT:    s_add_i32 s5, s5, s10
; GFX942-NEXT:    s_sub_i32 s14, s7, s5
; GFX942-NEXT:    s_mul_i32 s10, s12, s1
; GFX942-NEXT:    s_sub_u32 s15, s6, s10
; GFX942-NEXT:    s_cselect_b64 s[10:11], -1, 0
; GFX942-NEXT:    s_subb_u32 s14, s14, s13
; GFX942-NEXT:    s_sub_u32 s16, s15, s12
; GFX942-NEXT:    s_subb_u32 s14, s14, 0
; GFX942-NEXT:    s_cmp_ge_u32 s14, s13
; GFX942-NEXT:    s_cselect_b32 s17, -1, 0
; GFX942-NEXT:    s_cmp_ge_u32 s16, s12
; GFX942-NEXT:    s_cselect_b32 s16, -1, 0
; GFX942-NEXT:    s_cmp_eq_u32 s14, s13
; GFX942-NEXT:    s_cselect_b32 s14, s16, s17
; GFX942-NEXT:    s_add_u32 s16, s1, 1
; GFX942-NEXT:    s_addc_u32 s17, s3, 0
; GFX942-NEXT:    s_add_u32 s18, s1, 2
; GFX942-NEXT:    s_addc_u32 s19, s3, 0
; GFX942-NEXT:    s_cmp_lg_u32 s14, 0
; GFX942-NEXT:    s_cselect_b32 s14, s18, s16
; GFX942-NEXT:    s_cselect_b32 s16, s19, s17
; GFX942-NEXT:    s_cmp_lg_u64 s[10:11], 0
; GFX942-NEXT:    s_subb_u32 s5, s7, s5
; GFX942-NEXT:    s_cmp_ge_u32 s5, s13
; GFX942-NEXT:    s_cselect_b32 s10, -1, 0
; GFX942-NEXT:    s_cmp_ge_u32 s15, s12
; GFX942-NEXT:    s_cselect_b32 s11, -1, 0
; GFX942-NEXT:    s_cmp_eq_u32 s5, s13
; GFX942-NEXT:    s_cselect_b32 s5, s11, s10
; GFX942-NEXT:    s_cmp_lg_u32 s5, 0
; GFX942-NEXT:    s_cselect_b32 s11, s16, s3
; GFX942-NEXT:    s_cselect_b32 s10, s14, s1
; GFX942-NEXT:    s_cbranch_execnz .LBB0_3
; GFX942-NEXT:  .LBB0_2:
; GFX942-NEXT:    v_cvt_f32_u32_e32 v0, s12
; GFX942-NEXT:    s_sub_i32 s1, 0, s12
; GFX942-NEXT:    s_mov_b32 s11, 0
; GFX942-NEXT:    v_rcp_iflag_f32_e32 v0, v0
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX942-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_readfirstlane_b32 s3, v0
; GFX942-NEXT:    s_mul_i32 s1, s1, s3
; GFX942-NEXT:    s_mul_hi_u32 s1, s3, s1
; GFX942-NEXT:    s_add_i32 s3, s3, s1
; GFX942-NEXT:    s_mul_hi_u32 s1, s6, s3
; GFX942-NEXT:    s_mul_i32 s5, s1, s12
; GFX942-NEXT:    s_sub_i32 s5, s6, s5
; GFX942-NEXT:    s_add_i32 s3, s1, 1
; GFX942-NEXT:    s_sub_i32 s8, s5, s12
; GFX942-NEXT:    s_cmp_ge_u32 s5, s12
; GFX942-NEXT:    s_cselect_b32 s1, s3, s1
; GFX942-NEXT:    s_cselect_b32 s5, s8, s5
; GFX942-NEXT:    s_add_i32 s3, s1, 1
; GFX942-NEXT:    s_cmp_ge_u32 s5, s12
; GFX942-NEXT:    s_cselect_b32 s10, s3, s1
; GFX942-NEXT:  .LBB0_3:
; GFX942-NEXT:    s_ashr_i32 s1, s0, 31
; GFX942-NEXT:    s_add_u32 s3, s10, 15
; GFX942-NEXT:    s_addc_u32 s5, s11, 0
; GFX942-NEXT:    s_and_b32 s3, s3, -16
; GFX942-NEXT:    s_mul_i32 s1, s3, s1
; GFX942-NEXT:    s_mul_hi_u32 s8, s3, s0
; GFX942-NEXT:    s_add_i32 s1, s8, s1
; GFX942-NEXT:    s_mul_i32 s5, s5, s0
; GFX942-NEXT:    s_add_i32 s1, s1, s5
; GFX942-NEXT:    s_mul_i32 s3, s3, s0
; GFX942-NEXT:    v_cvt_f64_i32_e32 v[0:1], s1
; GFX942-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 32
; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], s3
; GFX942-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], s7
; GFX942-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 32
; GFX942-NEXT:    v_cvt_f64_u32_e32 v[4:5], s6
; GFX942-NEXT:    v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX942-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX942-NEXT:    v_trunc_f64_e32 v[0:1], v[0:1]
; GFX942-NEXT:    s_movk_i32 s0, 0xffe0
; GFX942-NEXT:    v_ldexp_f64 v[2:3], v[0:1], s0
; GFX942-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX942-NEXT:    v_fmac_f64_e32 v[0:1], 0xc1f00000, v[2:3]
; GFX942-NEXT:    v_cvt_u32_f64_e32 v0, v[0:1]
; GFX942-NEXT:    v_add_u32_e32 v1, s2, v0
; GFX942-NEXT:    v_add_u32_e32 v0, s4, v0
; GFX942-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX942-NEXT:    v_and_b32_e32 v0, 15, v0
; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX942-NEXT:    ;;#ASMSTART
; GFX942-NEXT:    ;;#ASMEND
; GFX942-NEXT:    s_endpgm
; GFX942-NEXT:  .Ltmp4:
; GFX942-NEXT:  .LBB0_4:
; GFX942-NEXT:    ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3
; GFX942-NEXT:    ; implicit-def: $sgpr10_sgpr11
; GFX942-NEXT:    .loc 0 0 0 is_stmt 0 ; <stdin>:0:0
; GFX942-NEXT:    s_branch .LBB0_2
entry:
  %0 = ptrtoint ptr addrspace(1) %dst.coerce to i64
  %1 = inttoptr i64 %0 to ptr
  %2 = ptrtoint ptr addrspace(1) %src.coerce to i64
    #dbg_value(ptr %1, !8, !DIExpression(DIOpArg(0, ptr)), !10)
  %3 = tail call noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x(), !dbg !10
  %4 = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr(), !dbg !10
  %5 = tail call i32 @llvm.amdgcn.workgroup.id.x(), !dbg !10
  %6 = load i32, ptr addrspace(4) %4, align 4, !dbg !10
  %7 = getelementptr inbounds nuw i8, ptr addrspace(4) %4, i64 12, !dbg !10
  %8 = load i16, ptr addrspace(4) %7, align 4, !dbg !10
  %conv.i.i = zext i16 %8 to i32, !dbg !10
  %conv = sext i32 %5 to i64, !dbg !10
  %conv6 = sext i32 %6 to i64, !dbg !10
  %div = udiv i64 %nElts, %conv6, !dbg !10
  %sub.i = add i64 %div, 15, !dbg !10
  %and.i = and i64 %sub.i, -16, !dbg !10
  %mul = mul i64 %and.i, %conv, !dbg !10
  %add8 = add nsw i32 %5, 1, !dbg !10
  %conv9 = sext i32 %add8 to i64, !dbg !10
  %mul13 = mul i64 %and.i, %conv9, !dbg !10
  %conv.i = sitofp i64 %mul to double, !dbg !10
  %conv1.i = uitofp i64 %nElts to double, !dbg !10
  %9 = tail call contract noundef double @llvm.minnum.f64(double %conv.i, double %conv1.i), !dbg !10
  %conv15 = fptosi double %9 to i64, !dbg !10
  %conv.i43 = sitofp i64 %mul13 to double, !dbg !10
  %10 = tail call contract noundef double @llvm.minnum.f64(double %conv.i43, double %conv1.i), !dbg !10
  %add.ptr18 = getelementptr inbounds i8, ptr %1, i64 %conv15, !dbg !10
  %rem = and i64 %redOpArg, 1, !dbg !10
  %cmp.not = icmp eq i64 %rem, 0, !dbg !10
  %rem21 = and i64 %redOpArg, 2, !dbg !10
  %cmp22.not = icmp eq i64 %rem21, 0, !dbg !10
  %rem26 = and i64 %redOpArg, 4, !dbg !10
  %cmp27.not = icmp eq i64 %rem26, 0, !dbg !10
  %11 = inttoptr i64 %redOpArg to ptr, !dbg !10
  %12 = load i64, ptr %11, align 8, !dbg !10
  %conv17 = fptosi double %10 to i64, !dbg !10
  %sub = sub nsw i64 %conv17, %conv15, !dbg !10
  %rem.i.i5354 = and i32 %3, 63, !dbg !10
  %cmp.i.i.not = icmp eq i32 %rem.i.i5354, 0, !dbg !10
  %13 = add i64 %2, %conv15, !dbg !10
  %14 = ptrtoint ptr %add.ptr18 to i64, !dbg !10
  %15 = or i64 %13, %14, !dbg !10
  %16 = and i64 %15, 15, !dbg !10
  %and1583.i.i = icmp ne i64 %16, 0, !dbg !10
  %17 = zext i1 %and1583.i.i to i32, !dbg !10
  %18 = tail call i32 asm sideeffect "", "=v,0"(i32 %17) #9, !dbg !10
  %19 = icmp ne i32 %18, 0, !dbg !10
  %20 = tail call i64 @llvm.amdgcn.ballot.i64(i1 %19), !dbg !10
  %.not.i.i = icmp eq i64 %20, 0, !dbg !10
  %div1.i.i.i555659 = lshr i32 %3, 6, !dbg !10
  %div8.i.i.i = sdiv i64 %sub, 4096, !dbg !10
  %mul9.i.i.i = shl nsw i64 %div8.i.i.i, 12, !dbg !10
  %sub12.i.i.i = sub nsw i64 %sub, %mul9.i.i.i, !dbg !10
  %conv13.i.i.i = zext nneg i32 %div1.i.i.i555659 to i64, !dbg !10
  %sub14.i.i.i = sub nsw i64 %div8.i.i.i, %conv13.i.i.i, !dbg !10
  %cmp30399.i.i.i = icmp sgt i64 %sub14.i.i.i, 0, !dbg !10
  ret void
}

attributes #0 = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3}
!0 = distinct !DICompileUnit(language: DW_LANG_OpenCL, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug)
!1 = !DIFile(filename: "<stdin>", directory: "/")
!2 = !{i32 7, !"Dwarf Version", i32 5}
!3 = !{i32 2, !"Debug Info Version", i32 3}
!4 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0)
!5 = !DISubroutineType(cc: DW_CC_LLVM_DeviceKernel, types: !6)
!6 = !{null}
!7 = !{i32 1024, i32 1, i32 1}
!8 = !DILocalVariable(name: "var", arg: 1, scope: !4, file: !1, line: 1, type: !9)
!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64)
!10 = !DILocation(line: 1, scope: !4)