; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s

define i32 @sbfx1(i32 %a) {
; CHECK-LABEL: sbfx1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    sbfx r0, r0, #7, #11
; CHECK-NEXT:    bx lr
	%t1 = lshr i32 %a, 7
	%t2 = trunc i32 %t1 to i11
	%t3 = sext i11 %t2 to i32
	ret i32 %t3
}

define i32 @ubfx1(i32 %a) {
; CHECK-LABEL: ubfx1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    ubfx r0, r0, #7, #11
; CHECK-NEXT:    bx lr
	%t1 = lshr i32 %a, 7
	%t2 = trunc i32 %t1 to i11
	%t3 = zext i11 %t2 to i32
	ret i32 %t3
}

define i32 @ubfx2(i32 %a) {
; CHECK-LABEL: ubfx2:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    ubfx r0, r0, #7, #11
; CHECK-NEXT:    bx lr
	%t1 = lshr i32 %a, 7
	%t2 = and i32 %t1, 2047
	ret i32 %t2
}

; rdar://12870177
define i32 @ubfx_opt(ptr nocapture %ctx, i32 %x) nounwind readonly ssp {
; CHECK-LABEL: ubfx_opt:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    ubfx r3, r1, #16, #8
; CHECK-NEXT:    lsr r2, r1, #24
; CHECK-NEXT:    ubfx r1, r1, #8, #8
; CHECK-NEXT:    ldr r2, [r0, r2, lsl #2]
; CHECK-NEXT:    ldr r3, [r0, r3, lsl #2]
; CHECK-NEXT:    ldr r0, [r0, r1, lsl #2]
; CHECK-NEXT:    add r2, r3, r2
; CHECK-NEXT:    add r0, r2, r0
; CHECK-NEXT:    bx lr
entry:
  %and = lshr i32 %x, 8
  %shr = and i32 %and, 255
  %and1 = lshr i32 %x, 16
  %shr2 = and i32 %and1, 255
  %shr4 = lshr i32 %x, 24
  %arrayidx = getelementptr inbounds i32, ptr %ctx, i32 %shr4
  %0 = load i32, ptr %arrayidx, align 4
  %arrayidx5 = getelementptr inbounds i32, ptr %ctx, i32 %shr2
  %1 = load i32, ptr %arrayidx5, align 4
  %add = add i32 %1, %0
  %arrayidx6 = getelementptr inbounds i32, ptr %ctx, i32 %shr
  %2 = load i32, ptr %arrayidx6, align 4
  %add7 = add i32 %add, %2
  ret i32 %add7
}

define i32 @ubfx3(i32 %a) {
; CHECK-LABEL: ubfx3:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    ubfx r0, r0, #11, #1
; CHECK-NEXT:    bx lr
	%t1 = and i32 %a, 2048
	%t2 = lshr i32 %t1, 11
	ret i32 %t2
}

define i32 @ubfx4(i32 %a) {
; CHECK-LABEL: ubfx4:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    ubfx r0, r0, #7, #3
; CHECK-NEXT:    bx lr
	%t1 = and i32 %a, 896
	%t2 = lshr i32 %t1, 7
	ret i32 %t2
}