; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s

define void @shufflevector_reverse_v16i8(ptr %res, ptr %a) nounwind {
; CHECK-LABEL: shufflevector_reverse_v16i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vshuf4i.w $vr0, $vr0, 27
; CHECK-NEXT:    vshuf4i.b $vr0, $vr0, 27
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <16 x i8>, ptr %a
  %b = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
  store <16 x i8> %b, ptr %res
  ret void
}

define void @shufflevector_reverse_v8i16(ptr %res, ptr %a) nounwind {
; CHECK-LABEL: shufflevector_reverse_v8i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vshuf4i.d $vr0, $vr0, 1
; CHECK-NEXT:    vshuf4i.h $vr0, $vr0, 27
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <8 x i16>, ptr %a
  %b = shufflevector <8 x i16> %va, <8 x i16> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
  store <8 x i16> %b, ptr %res
  ret void
}

define void @shufflevector_reverse_v4i32(ptr %res, ptr %a) nounwind {
; CHECK-LABEL: shufflevector_reverse_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vshuf4i.w $vr0, $vr0, 27
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <4 x i32>, ptr %a
  %b = shufflevector <4 x i32> %va, <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x i32> %b, ptr %res
  ret void
}

define void @shufflevector_reverse_v2i64(ptr %res, ptr %a) nounwind {
; CHECK-LABEL: shufflevector_reverse_v2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vshuf4i.d $vr0, $vr0, 1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <2 x i64>, ptr %a
  %b = shufflevector <2 x i64> %va, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
  store <2 x i64> %b, ptr %res
  ret void
}

define void @shufflevector_reverse_v4f32(ptr %res, ptr %a) nounwind {
; CHECK-LABEL: shufflevector_reverse_v4f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vshuf4i.w $vr0, $vr0, 27
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <4 x float>, ptr %a
  %b = shufflevector <4 x float> %va, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x float> %b, ptr %res
  ret void
}

define void @shufflevector_reverse_v2f64(ptr %res, ptr %a) nounwind {
; CHECK-LABEL: shufflevector_reverse_v2f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vshuf4i.d $vr0, $vr0, 1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <2 x double>, ptr %a
  %b = shufflevector <2 x double> %va, <2 x double> poison, <2 x i32> <i32 1, i32 0>
  store <2 x double> %b, ptr %res
  ret void
}