; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s

define <32 x i16> @backsmith_pure_7(<8 x i8> %conv) {
; CHECK-LABEL: backsmith_pure_7:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
; CHECK-NEXT:    vspltisw v3, 1
; CHECK-NEXT:    addis r4, r2, .LCPI0_5@toc@ha
; CHECK-NEXT:    li r5, 1
; CHECK-NEXT:    li r6, 0
; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
; CHECK-NEXT:    addi r4, r4, .LCPI0_5@toc@l
; CHECK-NEXT:    rldimi r6, r5, 32, 0
; CHECK-NEXT:    vupklsw v5, v3
; CHECK-NEXT:    mtvsrd v6, r5
; CHECK-NEXT:    li r5, 0
; CHECK-NEXT:    lxvd2x vs0, 0, r3
; CHECK-NEXT:    addis r3, r2, .LCPI0_3@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI0_3@toc@l
; CHECK-NEXT:    lxvd2x vs1, 0, r3
; CHECK-NEXT:    addis r3, r2, .LCPI0_4@toc@ha
; CHECK-NEXT:    xxmrgld v2, v2, v5
; CHECK-NEXT:    addi r3, r3, .LCPI0_4@toc@l
; CHECK-NEXT:    lxvd2x vs2, 0, r3
; CHECK-NEXT:    addis r3, r2, .LCPI0_6@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI0_6@toc@l
; CHECK-NEXT:    lxvd2x vs3, 0, r3
; CHECK-NEXT:    xxswapd v4, vs0
; CHECK-NEXT:    xxspltd vs0, v5, 1
; CHECK-NEXT:    mffprwz r3, f0
; CHECK-NEXT:    xxmrgld v3, v4, v5
; CHECK-NEXT:    xxswapd v0, vs1
; CHECK-NEXT:    xxswapd vs1, v3
; CHECK-NEXT:    vperm v0, v2, v4, v0
; CHECK-NEXT:    xxpermdi v4, v4, v2, 2
; CHECK-NEXT:    xxswapd v1, vs2
; CHECK-NEXT:    lxvd2x vs2, 0, r4
; CHECK-NEXT:    mffprwz r4, f0
; CHECK-NEXT:    rldimi r4, r3, 32, 0
; CHECK-NEXT:    addis r3, r2, .LCPI0_1@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI0_1@toc@l
; CHECK-NEXT:    lxvd2x vs0, 0, r3
; CHECK-NEXT:    mfvsrwz r3, v3
; CHECK-NEXT:    vperm v0, v5, v0, v1
; CHECK-NEXT:    mtvsrd v1, r5
; CHECK-NEXT:    addis r5, r2, .LCPI0_2@toc@ha
; CHECK-NEXT:    addi r5, r5, .LCPI0_2@toc@l
; CHECK-NEXT:    xxswapd v7, vs3
; CHECK-NEXT:    xxmrglw v8, v0, v0
; CHECK-NEXT:    xxmrghw v9, v0, v0
; CHECK-NEXT:    vperm v5, v2, v5, v7
; CHECK-NEXT:    xxswapd v7, v2
; CHECK-NEXT:    vpkudum v2, v2, v3
; CHECK-NEXT:    vmrghh v1, v1, v6
; CHECK-NEXT:    xxswapd v6, vs2
; CHECK-NEXT:    lxvd2x vs2, 0, r5
; CHECK-NEXT:    mffprwz r5, f1
; CHECK-NEXT:    vpkudum v4, v7, v4
; CHECK-NEXT:    vpkudum v7, v3, v7
; CHECK-NEXT:    mtfprd f1, r6
; CHECK-NEXT:    rldimi r5, r3, 32, 0
; CHECK-NEXT:    li r3, 1
; CHECK-NEXT:    vperm v6, v8, v0, v6
; CHECK-NEXT:    vmrghh v0, v9, v0
; CHECK-NEXT:    rldimi r3, r3, 32, 0
; CHECK-NEXT:    xxswapd v8, vs2
; CHECK-NEXT:    mtfprd f2, r5
; CHECK-NEXT:    xxswapd v3, vs0
; CHECK-NEXT:    mtfprd f0, r4
; CHECK-NEXT:    xxland v3, v4, v3
; CHECK-NEXT:    xxmrghd v9, vs1, vs0
; CHECK-NEXT:    mtfprd f0, r3
; CHECK-NEXT:    xxmrglw vs1, v0, v6
; CHECK-NEXT:    xxlxor v6, v6, v6
; CHECK-NEXT:    vperm v2, v6, v2, v8
; CHECK-NEXT:    vpkuwum v3, v3, v9
; CHECK-NEXT:    xxmrghd v0, vs0, vs2
; CHECK-NEXT:    xxspltw vs0, v1, 3
; CHECK-NEXT:    vperm v1, v6, v5, v8
; CHECK-NEXT:    vpkuwum v5, v2, v0
; CHECK-NEXT:    xxmrgld v2, vs1, vs0
; CHECK-NEXT:    vpkuwum v4, v7, v1
; CHECK-NEXT:    blr
entry:
  %0 = bitcast <8 x i8> %conv to i64
  %vecinit9 = insertelement <2 x i64> splat (i64 1), i64 %0, i64 1
  %shuffle = shufflevector <2 x i64> %vecinit9, <2 x i64> <i64 1, i64 0>, <32 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 1, i32 0, i32 3, i32 0, i32 0, i32 3, i32 2, i32 1, i32 2, i32 1, i32 3, i32 0, i32 3, i32 3, i32 1, i32 1, i32 0, i32 0, i32 2, i32 0, i32 2, i32 2, i32 2, i32 0, i32 2, i32 3, i32 1>
  %conv11 = trunc <32 x i64> %shuffle to <32 x i16>
  ret <32 x i16> %conv11
}