; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1100 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck --check-prefixes=CHECK-O0 %s
; RUN: llc -O1 -mtriple=amdgcn -mcpu=gfx1100 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck --check-prefixes=CHECK-O1 %s
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target triple = "amdgcn-amd-amdhsa"

define void @_QFPadd(ptr %0, ptr %1) #0 !dbg !12 {
  ; CHECK-O0-LABEL: name: _QFPadd
  ; CHECK-O0: bb.0 (%ir-block.2):
  ; CHECK-O0-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-O0-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK-O0-NEXT: {{  $}}
  ; CHECK-O0-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK-O0-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK-O0-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK-O0-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK-O0-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
  ; CHECK-O0-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
  ; CHECK-O0-NEXT:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
  ; CHECK-O0-NEXT:   DBG_VALUE [[COPY4]], 0, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8
  ; CHECK-O0-NEXT:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
  ; CHECK-O0-NEXT:   DBG_VALUE [[COPY5]], 0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8
  ; CHECK-O0-NEXT:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], debug-location !10
  ; CHECK-O0-NEXT:   [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY6]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0)
  ; CHECK-O0-NEXT:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], debug-location !10
  ; CHECK-O0-NEXT:   [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY7]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1)
  ; CHECK-O0-NEXT:   [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[FLAT_LOAD_DWORD1]], implicit $exec, debug-location !10
  ; CHECK-O0-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
  ; CHECK-O0-NEXT:   [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 killed [[V_CMP_GT_I32_e64_]], killed [[S_MOV_B32_]], implicit-def dead $scc, debug-location !10
  ; CHECK-O0-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[S_XOR_B32_]], implicit-def dead $scc, debug-location !10
  ; CHECK-O0-NEXT:   $vcc_lo = COPY [[S_AND_B32_]], debug-location !10
  ; CHECK-O0-NEXT:   S_CBRANCH_VCCNZ %bb.2, implicit $vcc, debug-location !10
  ; CHECK-O0-NEXT:   S_BRANCH %bb.1, debug-location !10
  ; CHECK-O0-NEXT: {{  $}}
  ; CHECK-O0-NEXT: bb.1 (%ir-block.6):
  ; CHECK-O0-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-O0-NEXT: {{  $}}
  ; CHECK-O0-NEXT:   [[FLAT_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0)
  ; CHECK-O0-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
  ; CHECK-O0-NEXT:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD2]], killed [[S_MOV_B32_1]], 0, implicit $exec, debug-location !11
  ; CHECK-O0-NEXT:   FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1)
  ; CHECK-O0-NEXT:   S_BRANCH %bb.3, debug-location !10
  ; CHECK-O0-NEXT: {{  $}}
  ; CHECK-O0-NEXT: bb.2 (%ir-block.9):
  ; CHECK-O0-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-O0-NEXT: {{  $}}
  ; CHECK-O0-NEXT:   [[FLAT_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (load (s32) from %ir.1)
  ; CHECK-O0-NEXT:   [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 1
  ; CHECK-O0-NEXT:   [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD3]], killed [[S_MOV_B32_2]], 0, implicit $exec, debug-location !12
  ; CHECK-O0-NEXT:   FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_1]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (store (s32) into %ir.1)
  ; CHECK-O0-NEXT:   S_BRANCH %bb.3, debug-location !10
  ; CHECK-O0-NEXT: {{  $}}
  ; CHECK-O0-NEXT: bb.3 (%ir-block.12):
  ; CHECK-O0-NEXT:   SI_RETURN debug-location !13
  ;
  ; CHECK-O1-LABEL: name: _QFPadd
  ; CHECK-O1: bb.0 (%ir-block.2):
  ; CHECK-O1-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-O1-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; CHECK-O1-NEXT: {{  $}}
  ; CHECK-O1-NEXT:   DBG_PHI $vgpr1, 6
  ; CHECK-O1-NEXT:   DBG_PHI $vgpr0, 5
  ; CHECK-O1-NEXT:   DBG_PHI $vgpr3, 3
  ; CHECK-O1-NEXT:   DBG_PHI $vgpr2, 2
  ; CHECK-O1-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; CHECK-O1-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; CHECK-O1-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK-O1-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK-O1-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1, debug-instr-number 1
  ; CHECK-O1-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1, debug-instr-number 4
  ; CHECK-O1-NEXT:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
  ; CHECK-O1-NEXT:   DBG_INSTR_REF !9, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(2, 0), dbg-instr-ref(3, 0), debug-location !8
  ; CHECK-O1-NEXT:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
  ; CHECK-O1-NEXT:   DBG_INSTR_REF !7, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(5, 0), dbg-instr-ref(6, 0), debug-location !8
  ; CHECK-O1-NEXT:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], debug-location !10
  ; CHECK-O1-NEXT:   [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY6]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0)
  ; CHECK-O1-NEXT:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], debug-location !10
  ; CHECK-O1-NEXT:   [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY7]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1)
  ; CHECK-O1-NEXT:   [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[FLAT_LOAD_DWORD1]], implicit $exec, debug-location !10
  ; CHECK-O1-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[V_CMP_LE_I32_e64_]], implicit-def dead $scc, debug-location !10
  ; CHECK-O1-NEXT:   $vcc_lo = COPY [[S_AND_B32_]], debug-location !10
  ; CHECK-O1-NEXT:   S_CBRANCH_VCCNZ %bb.2, implicit $vcc, debug-location !10
  ; CHECK-O1-NEXT:   S_BRANCH %bb.1, debug-location !10
  ; CHECK-O1-NEXT: {{  $}}
  ; CHECK-O1-NEXT: bb.1 (%ir-block.6):
  ; CHECK-O1-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-O1-NEXT: {{  $}}
  ; CHECK-O1-NEXT:   [[FLAT_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0)
  ; CHECK-O1-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
  ; CHECK-O1-NEXT:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD2]], killed [[S_MOV_B32_]], 0, implicit $exec, debug-location !11
  ; CHECK-O1-NEXT:   FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1)
  ; CHECK-O1-NEXT:   S_BRANCH %bb.3, debug-location !10
  ; CHECK-O1-NEXT: {{  $}}
  ; CHECK-O1-NEXT: bb.2 (%ir-block.9):
  ; CHECK-O1-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-O1-NEXT: {{  $}}
  ; CHECK-O1-NEXT:   [[FLAT_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (load (s32) from %ir.1)
  ; CHECK-O1-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
  ; CHECK-O1-NEXT:   [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD3]], killed [[S_MOV_B32_1]], 0, implicit $exec, debug-location !12
  ; CHECK-O1-NEXT:   FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_1]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (store (s32) into %ir.1)
  ; CHECK-O1-NEXT: {{  $}}
  ; CHECK-O1-NEXT: bb.3 (%ir-block.12):
  ; CHECK-O1-NEXT:   SI_RETURN debug-location !13
    #dbg_declare(ptr %0, !17, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !18)
    #dbg_declare(ptr %1, !19, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !18)
  %3 = load i32, ptr %0, align 4, !dbg !20
  %4 = load i32, ptr %1, align 4, !dbg !20
  %5 = icmp sgt i32 %3, %4, !dbg !20
  br i1 %5, label %6, label %9, !dbg !20

6:                                                ; preds = %2
  %7 = load i32, ptr %0, align 4, !dbg !21
  %8 = add i32 %7, 1, !dbg !21
  store i32 %8, ptr %1, align 4, !dbg !21
  br label %12, !dbg !20

9:                                                ; preds = %2
  %10 = load i32, ptr %1, align 4, !dbg !22
  %11 = add i32 %10, 1, !dbg !22
  store i32 %11, ptr %1, align 4, !dbg !22
  br label %12, !dbg !20

12:                                               ; preds = %9, %6
  ret void, !dbg !23
}


!llvm.module.flags = !{!2}
!llvm.dbg.cu = !{!6}

!2 = !{i32 2, !"Debug Info Version", i32 3}
!6 = distinct !DICompileUnit(language: DW_LANG_Fortran95, file: !7, producer: "flang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug)
!7 = !DIFile(filename: "target14.f90", directory: "")
!11 = !{i32 2, i32 0}
!12 = distinct !DISubprogram(name: "add", linkageName: "_QFPadd", scope: !7, file: !7, line: 16, type: !14, scopeLine: 16, spFlags: DISPFlagDefinition, unit: !6)
!14 = !DISubroutineType(cc: DW_CC_normal, types: !15)
!15 = !{null, !16, !16}
!16 = !DIBasicType(name: "integer", size: 32, encoding: DW_ATE_signed)
!17 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !7, line: 17, type: !16)
!18 = !DILocation(line: 16, column: 7, scope: !12)
!19 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !7, line: 17, type: !16)
!20 = !DILocation(line: 20, column: 7, scope: !12)
!21 = !DILocation(line: 21, column: 7, scope: !12)
!22 = !DILocation(line: 23, column: 7, scope: !12)
!23 = !DILocation(line: 25, column: 7, scope: !12)