; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 ; RUN: opt -S -force-vector-width=2 -force-vector-interleave=1 -passes=loop-vectorize -verify-loop-info -force-widen-divrem-via-masked-intrinsic=0 < %s | FileCheck %s ; RUN: opt -S -force-vector-width=1 -force-vector-interleave=2 -passes=loop-vectorize -verify-loop-info -force-widen-divrem-via-masked-intrinsic=0 < %s | FileCheck %s --check-prefix=UNROLL-NO-VF target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; Test predication of non-void instructions, specifically (i) that these ; instructions permit vectorization and (ii) the creation of an insertelement ; and a Phi node. We check the full 2-element sequence for all predicate instructions. define void @test(ptr nocapture %asd, ptr nocapture %aud, ; CHECK-LABEL: define void @test( ; CHECK-SAME: ptr captures(none) [[ASD:%.*]], ptr captures(none) [[AUD:%.*]], ptr captures(none) [[ASR:%.*]], ptr captures(none) [[AUR:%.*]]) { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD]], i64 512 ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[AUD]], i64 512 ; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[ASR]], i64 512 ; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[AUR]], i64 512 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; CHECK-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP2]] ; CHECK-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP]] ; CHECK-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]] ; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]] ; CHECK-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP3]] ; CHECK-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP]] ; CHECK-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]] ; CHECK-NEXT: [[CONFLICT_RDX10:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT9]] ; CHECK-NEXT: [[BOUND011:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP2]] ; CHECK-NEXT: [[BOUND112:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP1]] ; CHECK-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]] ; CHECK-NEXT: [[CONFLICT_RDX14:%.*]] = or i1 [[CONFLICT_RDX10]], [[FOUND_CONFLICT13]] ; CHECK-NEXT: [[BOUND015:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP3]] ; CHECK-NEXT: [[BOUND116:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP1]] ; CHECK-NEXT: [[FOUND_CONFLICT17:%.*]] = and i1 [[BOUND015]], [[BOUND116]] ; CHECK-NEXT: [[CONFLICT_RDX18:%.*]] = or i1 [[CONFLICT_RDX14]], [[FOUND_CONFLICT17]] ; CHECK-NEXT: [[BOUND019:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP3]] ; CHECK-NEXT: [[BOUND120:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP2]] ; CHECK-NEXT: [[FOUND_CONFLICT21:%.*]] = and i1 [[BOUND019]], [[BOUND120]] ; CHECK-NEXT: [[CONFLICT_RDX22:%.*]] = or i1 [[CONFLICT_RDX18]], [[FOUND_CONFLICT21]] ; CHECK-NEXT: br i1 [[CONFLICT_RDX22]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_UREM_CONTINUE27:.*]] ] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP0]], align 4, !alias.scope [[META5:![0-9]+]], !noalias [[META8:![0-9]+]] ; CHECK-NEXT: [[WIDE_LOAD23:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4, !alias.scope [[META12:![0-9]+]], !noalias [[META13:![0-9]+]] ; CHECK-NEXT: [[WIDE_LOAD24:%.*]] = load <2 x i32>, ptr [[TMP2]], align 4, !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]] ; CHECK-NEXT: [[WIDE_LOAD25:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4, !alias.scope [[META15]] ; CHECK-NEXT: [[TMP4:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], splat (i32 23) ; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i32> [[WIDE_LOAD23]], splat (i32 24) ; CHECK-NEXT: [[TMP6:%.*]] = add nsw <2 x i32> [[WIDE_LOAD24]], splat (i32 25) ; CHECK-NEXT: [[TMP7:%.*]] = add nsw <2 x i32> [[WIDE_LOAD25]], splat (i32 26) ; CHECK-NEXT: [[TMP8:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], splat (i32 100) ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP8]], i64 0 ; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_UREM_IF:.*]], label %[[PRED_UREM_CONTINUE:.*]] ; CHECK: [[PRED_UREM_IF]]: ; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[TMP4]], i64 0 ; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 0 ; CHECK-NEXT: [[TMP12:%.*]] = sdiv i32 [[TMP10]], [[TMP11]] ; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> poison, i32 [[TMP12]], i64 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP5]], i64 0 ; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[WIDE_LOAD23]], i64 0 ; CHECK-NEXT: [[TMP16:%.*]] = udiv i32 [[TMP14]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x i32> poison, i32 [[TMP16]], i64 0 ; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i32> [[TMP6]], i64 0 ; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[WIDE_LOAD24]], i64 0 ; CHECK-NEXT: [[TMP20:%.*]] = srem i32 [[TMP18]], [[TMP19]] ; CHECK-NEXT: [[TMP21:%.*]] = insertelement <2 x i32> poison, i32 [[TMP20]], i64 0 ; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[TMP7]], i64 0 ; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[WIDE_LOAD25]], i64 0 ; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[TMP22]], [[TMP23]] ; CHECK-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> poison, i32 [[TMP24]], i64 0 ; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE]] ; CHECK: [[PRED_UREM_CONTINUE]]: ; CHECK-NEXT: [[TMP26:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP13]], %[[PRED_UREM_IF]] ] ; CHECK-NEXT: [[TMP27:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP17]], %[[PRED_UREM_IF]] ] ; CHECK-NEXT: [[TMP28:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP21]], %[[PRED_UREM_IF]] ] ; CHECK-NEXT: [[TMP29:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP25]], %[[PRED_UREM_IF]] ] ; CHECK-NEXT: [[TMP30:%.*]] = extractelement <2 x i1> [[TMP8]], i64 1 ; CHECK-NEXT: br i1 [[TMP30]], label %[[PRED_UREM_IF26:.*]], label %[[PRED_UREM_CONTINUE27]] ; CHECK: [[PRED_UREM_IF26]]: ; CHECK-NEXT: [[TMP31:%.*]] = extractelement <2 x i32> [[TMP4]], i64 1 ; CHECK-NEXT: [[TMP32:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 1 ; CHECK-NEXT: [[TMP33:%.*]] = sdiv i32 [[TMP31]], [[TMP32]] ; CHECK-NEXT: [[TMP34:%.*]] = insertelement <2 x i32> [[TMP26]], i32 [[TMP33]], i64 1 ; CHECK-NEXT: [[TMP35:%.*]] = extractelement <2 x i32> [[TMP5]], i64 1 ; CHECK-NEXT: [[TMP36:%.*]] = extractelement <2 x i32> [[WIDE_LOAD23]], i64 1 ; CHECK-NEXT: [[TMP37:%.*]] = udiv i32 [[TMP35]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = insertelement <2 x i32> [[TMP27]], i32 [[TMP37]], i64 1 ; CHECK-NEXT: [[TMP39:%.*]] = extractelement <2 x i32> [[TMP6]], i64 1 ; CHECK-NEXT: [[TMP40:%.*]] = extractelement <2 x i32> [[WIDE_LOAD24]], i64 1 ; CHECK-NEXT: [[TMP41:%.*]] = srem i32 [[TMP39]], [[TMP40]] ; CHECK-NEXT: [[TMP42:%.*]] = insertelement <2 x i32> [[TMP28]], i32 [[TMP41]], i64 1 ; CHECK-NEXT: [[TMP43:%.*]] = extractelement <2 x i32> [[TMP7]], i64 1 ; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[WIDE_LOAD25]], i64 1 ; CHECK-NEXT: [[TMP45:%.*]] = urem i32 [[TMP43]], [[TMP44]] ; CHECK-NEXT: [[TMP46:%.*]] = insertelement <2 x i32> [[TMP29]], i32 [[TMP45]], i64 1 ; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE27]] ; CHECK: [[PRED_UREM_CONTINUE27]]: ; CHECK-NEXT: [[TMP47:%.*]] = phi <2 x i32> [ [[TMP26]], %[[PRED_UREM_CONTINUE]] ], [ [[TMP34]], %[[PRED_UREM_IF26]] ] ; CHECK-NEXT: [[TMP48:%.*]] = phi <2 x i32> [ [[TMP27]], %[[PRED_UREM_CONTINUE]] ], [ [[TMP38]], %[[PRED_UREM_IF26]] ] ; CHECK-NEXT: [[TMP49:%.*]] = phi <2 x i32> [ [[TMP28]], %[[PRED_UREM_CONTINUE]] ], [ [[TMP42]], %[[PRED_UREM_IF26]] ] ; CHECK-NEXT: [[TMP50:%.*]] = phi <2 x i32> [ [[TMP29]], %[[PRED_UREM_CONTINUE]] ], [ [[TMP46]], %[[PRED_UREM_IF26]] ] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP8]], <2 x i32> [[TMP47]], <2 x i32> [[TMP4]] ; CHECK-NEXT: [[PREDPHI28:%.*]] = select <2 x i1> [[TMP8]], <2 x i32> [[TMP48]], <2 x i32> [[TMP5]] ; CHECK-NEXT: [[PREDPHI29:%.*]] = select <2 x i1> [[TMP8]], <2 x i32> [[TMP49]], <2 x i32> [[TMP6]] ; CHECK-NEXT: [[PREDPHI30:%.*]] = select <2 x i1> [[TMP8]], <2 x i32> [[TMP50]], <2 x i32> [[TMP7]] ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP0]], align 4, !alias.scope [[META5]], !noalias [[META8]] ; CHECK-NEXT: store <2 x i32> [[PREDPHI28]], ptr [[TMP1]], align 4, !alias.scope [[META12]], !noalias [[META13]] ; CHECK-NEXT: store <2 x i32> [[PREDPHI29]], ptr [[TMP2]], align 4, !alias.scope [[META14]], !noalias [[META15]] ; CHECK-NEXT: store <2 x i32> [[PREDPHI30]], ptr [[TMP3]], align 4, !alias.scope [[META15]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP51:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 ; CHECK-NEXT: br i1 [[TMP51]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: br label %[[FOR_BODY:.*]] ; CHECK: [[FOR_COND_CLEANUP]]: ; CHECK-NEXT: ret void ; CHECK: [[FOR_BODY]]: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[IF_END:.*]] ] ; CHECK-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[IUD:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[ISR:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[IUR:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4 ; CHECK-NEXT: [[LUD:%.*]] = load i32, ptr [[IUD]], align 4 ; CHECK-NEXT: [[LSR:%.*]] = load i32, ptr [[ISR]], align 4 ; CHECK-NEXT: [[LUR:%.*]] = load i32, ptr [[IUR]], align 4 ; CHECK-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23 ; CHECK-NEXT: [[PUD:%.*]] = add nsw i32 [[LUD]], 24 ; CHECK-NEXT: [[PSR:%.*]] = add nsw i32 [[LSR]], 25 ; CHECK-NEXT: [[PUR:%.*]] = add nsw i32 [[LUR]], 26 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100 ; CHECK-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END]] ; CHECK: [[IF_THEN]]: ; CHECK-NEXT: [[RSD:%.*]] = sdiv i32 [[PSD]], [[LSD]] ; CHECK-NEXT: [[RUD:%.*]] = udiv i32 [[PUD]], [[LUD]] ; CHECK-NEXT: [[RSR:%.*]] = srem i32 [[PSR]], [[LSR]] ; CHECK-NEXT: [[RUR:%.*]] = urem i32 [[PUR]], [[LUR]] ; CHECK-NEXT: br label %[[IF_END]] ; CHECK: [[IF_END]]: ; CHECK-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], %[[IF_THEN]] ], [ [[PSD]], %[[FOR_BODY]] ] ; CHECK-NEXT: [[YUD_0:%.*]] = phi i32 [ [[RUD]], %[[IF_THEN]] ], [ [[PUD]], %[[FOR_BODY]] ] ; CHECK-NEXT: [[YSR_0:%.*]] = phi i32 [ [[RSR]], %[[IF_THEN]] ], [ [[PSR]], %[[FOR_BODY]] ] ; CHECK-NEXT: [[YUR_0:%.*]] = phi i32 [ [[RUR]], %[[IF_THEN]] ], [ [[PUR]], %[[FOR_BODY]] ] ; CHECK-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4 ; CHECK-NEXT: store i32 [[YUD_0]], ptr [[IUD]], align 4 ; CHECK-NEXT: store i32 [[YSR_0]], ptr [[ISR]], align 4 ; CHECK-NEXT: store i32 [[YUR_0]], ptr [[IUR]], align 4 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128 ; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]] ; ; UNROLL-NO-VF-LABEL: define void @test( ; UNROLL-NO-VF-SAME: ptr captures(none) [[ASD:%.*]], ptr captures(none) [[AUD:%.*]], ptr captures(none) [[ASR:%.*]], ptr captures(none) [[AUR:%.*]]) { ; UNROLL-NO-VF-NEXT: [[ENTRY:.*:]] ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; UNROLL-NO-VF: [[VECTOR_MEMCHECK]]: ; UNROLL-NO-VF-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD]], i64 512 ; UNROLL-NO-VF-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[AUD]], i64 512 ; UNROLL-NO-VF-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[ASR]], i64 512 ; UNROLL-NO-VF-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[AUR]], i64 512 ; UNROLL-NO-VF-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]] ; UNROLL-NO-VF-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; UNROLL-NO-VF-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP2]] ; UNROLL-NO-VF-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]] ; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]] ; UNROLL-NO-VF-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP3]] ; UNROLL-NO-VF-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]] ; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX10:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT9]] ; UNROLL-NO-VF-NEXT: [[BOUND011:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP2]] ; UNROLL-NO-VF-NEXT: [[BOUND112:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP1]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]] ; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX14:%.*]] = or i1 [[CONFLICT_RDX10]], [[FOUND_CONFLICT13]] ; UNROLL-NO-VF-NEXT: [[BOUND015:%.*]] = icmp ult ptr [[AUD]], [[SCEVGEP3]] ; UNROLL-NO-VF-NEXT: [[BOUND116:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP1]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT17:%.*]] = and i1 [[BOUND015]], [[BOUND116]] ; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX18:%.*]] = or i1 [[CONFLICT_RDX14]], [[FOUND_CONFLICT17]] ; UNROLL-NO-VF-NEXT: [[BOUND019:%.*]] = icmp ult ptr [[ASR]], [[SCEVGEP3]] ; UNROLL-NO-VF-NEXT: [[BOUND120:%.*]] = icmp ult ptr [[AUR]], [[SCEVGEP2]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT21:%.*]] = and i1 [[BOUND019]], [[BOUND120]] ; UNROLL-NO-VF-NEXT: [[CONFLICT_RDX22:%.*]] = or i1 [[CONFLICT_RDX18]], [[FOUND_CONFLICT21]] ; UNROLL-NO-VF-NEXT: br i1 [[CONFLICT_RDX22]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; UNROLL-NO-VF: [[VECTOR_PH]]: ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_BODY:.*]] ; UNROLL-NO-VF: [[VECTOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_UREM_CONTINUE24:.*]] ] ; UNROLL-NO-VF-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4, !alias.scope [[META5:![0-9]+]], !noalias [[META8:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP2]], align 4, !alias.scope [[META5]], !noalias [[META8]] ; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4, !alias.scope [[META12:![0-9]+]], !noalias [[META13:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP4]], align 4, !alias.scope [[META12]], !noalias [[META13]] ; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP6]], align 4, !alias.scope [[META14]], !noalias [[META15]] ; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP7]], align 4, !alias.scope [[META15]] ; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP8]], align 4, !alias.scope [[META15]] ; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = add nsw i32 [[TMP9]], 23 ; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = add nsw i32 [[TMP10]], 23 ; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP11]], 24 ; UNROLL-NO-VF-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP12]], 24 ; UNROLL-NO-VF-NEXT: [[TMP21:%.*]] = add nsw i32 [[TMP13]], 25 ; UNROLL-NO-VF-NEXT: [[TMP22:%.*]] = add nsw i32 [[TMP14]], 25 ; UNROLL-NO-VF-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP15]], 26 ; UNROLL-NO-VF-NEXT: [[TMP24:%.*]] = add nsw i32 [[TMP16]], 26 ; UNROLL-NO-VF-NEXT: [[TMP25:%.*]] = icmp slt i32 [[TMP9]], 100 ; UNROLL-NO-VF-NEXT: [[TMP26:%.*]] = icmp slt i32 [[TMP10]], 100 ; UNROLL-NO-VF-NEXT: br i1 [[TMP25]], label %[[PRED_UREM_IF:.*]], label %[[PRED_UREM_CONTINUE:.*]] ; UNROLL-NO-VF: [[PRED_UREM_IF]]: ; UNROLL-NO-VF-NEXT: [[TMP27:%.*]] = sdiv i32 [[TMP17]], [[TMP9]] ; UNROLL-NO-VF-NEXT: [[TMP28:%.*]] = udiv i32 [[TMP19]], [[TMP11]] ; UNROLL-NO-VF-NEXT: [[TMP29:%.*]] = srem i32 [[TMP21]], [[TMP13]] ; UNROLL-NO-VF-NEXT: [[TMP30:%.*]] = urem i32 [[TMP23]], [[TMP15]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_UREM_CONTINUE]] ; UNROLL-NO-VF: [[PRED_UREM_CONTINUE]]: ; UNROLL-NO-VF-NEXT: [[TMP31:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP27]], %[[PRED_UREM_IF]] ] ; UNROLL-NO-VF-NEXT: [[TMP32:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP28]], %[[PRED_UREM_IF]] ] ; UNROLL-NO-VF-NEXT: [[TMP33:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP29]], %[[PRED_UREM_IF]] ] ; UNROLL-NO-VF-NEXT: [[TMP34:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP30]], %[[PRED_UREM_IF]] ] ; UNROLL-NO-VF-NEXT: br i1 [[TMP26]], label %[[PRED_UREM_IF23:.*]], label %[[PRED_UREM_CONTINUE24]] ; UNROLL-NO-VF: [[PRED_UREM_IF23]]: ; UNROLL-NO-VF-NEXT: [[TMP35:%.*]] = sdiv i32 [[TMP18]], [[TMP10]] ; UNROLL-NO-VF-NEXT: [[TMP36:%.*]] = udiv i32 [[TMP20]], [[TMP12]] ; UNROLL-NO-VF-NEXT: [[TMP37:%.*]] = srem i32 [[TMP22]], [[TMP14]] ; UNROLL-NO-VF-NEXT: [[TMP38:%.*]] = urem i32 [[TMP24]], [[TMP16]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_UREM_CONTINUE24]] ; UNROLL-NO-VF: [[PRED_UREM_CONTINUE24]]: ; UNROLL-NO-VF-NEXT: [[TMP39:%.*]] = phi i32 [ poison, %[[PRED_UREM_CONTINUE]] ], [ [[TMP35]], %[[PRED_UREM_IF23]] ] ; UNROLL-NO-VF-NEXT: [[TMP40:%.*]] = phi i32 [ poison, %[[PRED_UREM_CONTINUE]] ], [ [[TMP36]], %[[PRED_UREM_IF23]] ] ; UNROLL-NO-VF-NEXT: [[TMP41:%.*]] = phi i32 [ poison, %[[PRED_UREM_CONTINUE]] ], [ [[TMP37]], %[[PRED_UREM_IF23]] ] ; UNROLL-NO-VF-NEXT: [[TMP42:%.*]] = phi i32 [ poison, %[[PRED_UREM_CONTINUE]] ], [ [[TMP38]], %[[PRED_UREM_IF23]] ] ; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP25]], i32 [[TMP31]], i32 [[TMP17]] ; UNROLL-NO-VF-NEXT: [[PREDPHI25:%.*]] = select i1 [[TMP26]], i32 [[TMP39]], i32 [[TMP18]] ; UNROLL-NO-VF-NEXT: [[PREDPHI26:%.*]] = select i1 [[TMP25]], i32 [[TMP32]], i32 [[TMP19]] ; UNROLL-NO-VF-NEXT: [[PREDPHI27:%.*]] = select i1 [[TMP26]], i32 [[TMP40]], i32 [[TMP20]] ; UNROLL-NO-VF-NEXT: [[PREDPHI28:%.*]] = select i1 [[TMP25]], i32 [[TMP33]], i32 [[TMP21]] ; UNROLL-NO-VF-NEXT: [[PREDPHI29:%.*]] = select i1 [[TMP26]], i32 [[TMP41]], i32 [[TMP22]] ; UNROLL-NO-VF-NEXT: [[PREDPHI30:%.*]] = select i1 [[TMP25]], i32 [[TMP34]], i32 [[TMP23]] ; UNROLL-NO-VF-NEXT: [[PREDPHI31:%.*]] = select i1 [[TMP26]], i32 [[TMP42]], i32 [[TMP24]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI]], ptr [[TMP1]], align 4, !alias.scope [[META5]], !noalias [[META8]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI25]], ptr [[TMP2]], align 4, !alias.scope [[META5]], !noalias [[META8]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI26]], ptr [[TMP3]], align 4, !alias.scope [[META12]], !noalias [[META13]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI27]], ptr [[TMP4]], align 4, !alias.scope [[META12]], !noalias [[META13]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI28]], ptr [[TMP5]], align 4, !alias.scope [[META14]], !noalias [[META15]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI29]], ptr [[TMP6]], align 4, !alias.scope [[META14]], !noalias [[META15]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI30]], ptr [[TMP7]], align 4, !alias.scope [[META15]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI31]], ptr [[TMP8]], align 4, !alias.scope [[META15]] ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP43:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 ; UNROLL-NO-VF-NEXT: br i1 [[TMP43]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] ; UNROLL-NO-VF: [[MIDDLE_BLOCK]]: ; UNROLL-NO-VF-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; UNROLL-NO-VF: [[SCALAR_PH]]: ; UNROLL-NO-VF-NEXT: br label %[[FOR_BODY:.*]] ; UNROLL-NO-VF: [[FOR_COND_CLEANUP]]: ; UNROLL-NO-VF-NEXT: ret void ; UNROLL-NO-VF: [[FOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[IF_END:.*]] ] ; UNROLL-NO-VF-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[IUD:%.*]] = getelementptr inbounds i32, ptr [[AUD]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[ISR:%.*]] = getelementptr inbounds i32, ptr [[ASR]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[IUR:%.*]] = getelementptr inbounds i32, ptr [[AUR]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4 ; UNROLL-NO-VF-NEXT: [[LUD:%.*]] = load i32, ptr [[IUD]], align 4 ; UNROLL-NO-VF-NEXT: [[LSR:%.*]] = load i32, ptr [[ISR]], align 4 ; UNROLL-NO-VF-NEXT: [[LUR:%.*]] = load i32, ptr [[IUR]], align 4 ; UNROLL-NO-VF-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23 ; UNROLL-NO-VF-NEXT: [[PUD:%.*]] = add nsw i32 [[LUD]], 24 ; UNROLL-NO-VF-NEXT: [[PSR:%.*]] = add nsw i32 [[LSR]], 25 ; UNROLL-NO-VF-NEXT: [[PUR:%.*]] = add nsw i32 [[LUR]], 26 ; UNROLL-NO-VF-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100 ; UNROLL-NO-VF-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END]] ; UNROLL-NO-VF: [[IF_THEN]]: ; UNROLL-NO-VF-NEXT: [[RSD:%.*]] = sdiv i32 [[PSD]], [[LSD]] ; UNROLL-NO-VF-NEXT: [[RUD:%.*]] = udiv i32 [[PUD]], [[LUD]] ; UNROLL-NO-VF-NEXT: [[RSR:%.*]] = srem i32 [[PSR]], [[LSR]] ; UNROLL-NO-VF-NEXT: [[RUR:%.*]] = urem i32 [[PUR]], [[LUR]] ; UNROLL-NO-VF-NEXT: br label %[[IF_END]] ; UNROLL-NO-VF: [[IF_END]]: ; UNROLL-NO-VF-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], %[[IF_THEN]] ], [ [[PSD]], %[[FOR_BODY]] ] ; UNROLL-NO-VF-NEXT: [[YUD_0:%.*]] = phi i32 [ [[RUD]], %[[IF_THEN]] ], [ [[PUD]], %[[FOR_BODY]] ] ; UNROLL-NO-VF-NEXT: [[YSR_0:%.*]] = phi i32 [ [[RSR]], %[[IF_THEN]] ], [ [[PSR]], %[[FOR_BODY]] ] ; UNROLL-NO-VF-NEXT: [[YUR_0:%.*]] = phi i32 [ [[RUR]], %[[IF_THEN]] ], [ [[PUR]], %[[FOR_BODY]] ] ; UNROLL-NO-VF-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4 ; UNROLL-NO-VF-NEXT: store i32 [[YUD_0]], ptr [[IUD]], align 4 ; UNROLL-NO-VF-NEXT: store i32 [[YSR_0]], ptr [[ISR]], align 4 ; UNROLL-NO-VF-NEXT: store i32 [[YUR_0]], ptr [[IUR]], align 4 ; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128 ; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]] ; ptr nocapture %asr, ptr nocapture %aur) { entry: br label %for.body for.cond.cleanup: ret void for.body: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ] %isd = getelementptr inbounds i32, ptr %asd, i64 %indvars.iv %iud = getelementptr inbounds i32, ptr %aud, i64 %indvars.iv %isr = getelementptr inbounds i32, ptr %asr, i64 %indvars.iv %iur = getelementptr inbounds i32, ptr %aur, i64 %indvars.iv %lsd = load i32, ptr %isd, align 4 %lud = load i32, ptr %iud, align 4 %lsr = load i32, ptr %isr, align 4 %lur = load i32, ptr %iur, align 4 %psd = add nsw i32 %lsd, 23 %pud = add nsw i32 %lud, 24 %psr = add nsw i32 %lsr, 25 %pur = add nsw i32 %lur, 26 %cmp1 = icmp slt i32 %lsd, 100 br i1 %cmp1, label %if.then, label %if.end if.then: %rsd = sdiv i32 %psd, %lsd %rud = udiv i32 %pud, %lud %rsr = srem i32 %psr, %lsr %rur = urem i32 %pur, %lur br label %if.end if.end: %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ] %yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ] %ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ] %yur.0 = phi i32 [ %rur, %if.then ], [ %pur, %for.body ] store i32 %ysd.0, ptr %isd, align 4 store i32 %yud.0, ptr %iud, align 4 store i32 %ysr.0, ptr %isr, align 4 store i32 %yur.0, ptr %iur, align 4 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 128 br i1 %exitcond, label %for.cond.cleanup, label %for.body } define void @test_scalar2scalar(ptr nocapture %asd, ptr nocapture %bsd) { ; CHECK-LABEL: define void @test_scalar2scalar( ; CHECK-SAME: ptr captures(none) [[ASD:%.*]], ptr captures(none) [[BSD:%.*]]) { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD]], i64 512 ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD]], i64 512 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE4:.*]] ] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP0]], align 4, !alias.scope [[META20:![0-9]+]], !noalias [[META23:![0-9]+]] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4, !alias.scope [[META23]] ; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], splat (i32 23) ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], splat (i32 100) ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i64 0 ; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]] ; CHECK: [[PRED_SDIV_IF]]: ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0 ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 0 ; CHECK-NEXT: [[TMP7:%.*]] = sdiv i32 [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i64 0 ; CHECK-NEXT: [[TMP9:%.*]] = sdiv i32 [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> poison, i32 [[TMP9]], i64 0 ; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]] ; CHECK: [[PRED_SDIV_CONTINUE]]: ; CHECK-NEXT: [[TMP11:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP10]], %[[PRED_SDIV_IF]] ] ; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP3]], i64 1 ; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_SDIV_IF3:.*]], label %[[PRED_SDIV_CONTINUE4]] ; CHECK: [[PRED_SDIV_IF3]]: ; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1 ; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 1 ; CHECK-NEXT: [[TMP15:%.*]] = sdiv i32 [[TMP13]], [[TMP14]] ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i64 1 ; CHECK-NEXT: [[TMP17:%.*]] = sdiv i32 [[TMP16]], [[TMP15]] ; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i32> [[TMP11]], i32 [[TMP17]], i64 1 ; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE4]] ; CHECK: [[PRED_SDIV_CONTINUE4]]: ; CHECK-NEXT: [[TMP19:%.*]] = phi <2 x i32> [ [[TMP11]], %[[PRED_SDIV_CONTINUE]] ], [ [[TMP18]], %[[PRED_SDIV_IF3]] ] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP19]], <2 x i32> [[TMP2]] ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP0]], align 4, !alias.scope [[META20]], !noalias [[META23]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 ; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: br label %[[FOR_BODY:.*]] ; CHECK: [[FOR_COND_CLEANUP]]: ; CHECK-NEXT: ret void ; CHECK: [[FOR_BODY]]: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[IF_END:.*]] ] ; CHECK-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4 ; CHECK-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4 ; CHECK-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100 ; CHECK-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END]] ; CHECK: [[IF_THEN]]: ; CHECK-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]] ; CHECK-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]] ; CHECK-NEXT: br label %[[IF_END]] ; CHECK: [[IF_END]]: ; CHECK-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], %[[IF_THEN]] ], [ [[PSD]], %[[FOR_BODY]] ] ; CHECK-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128 ; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]] ; ; UNROLL-NO-VF-LABEL: define void @test_scalar2scalar( ; UNROLL-NO-VF-SAME: ptr captures(none) [[ASD:%.*]], ptr captures(none) [[BSD:%.*]]) { ; UNROLL-NO-VF-NEXT: [[ENTRY:.*:]] ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; UNROLL-NO-VF: [[VECTOR_MEMCHECK]]: ; UNROLL-NO-VF-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD]], i64 512 ; UNROLL-NO-VF-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD]], i64 512 ; UNROLL-NO-VF-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]] ; UNROLL-NO-VF-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; UNROLL-NO-VF-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; UNROLL-NO-VF: [[VECTOR_PH]]: ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_BODY:.*]] ; UNROLL-NO-VF: [[VECTOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE3:.*]] ] ; UNROLL-NO-VF-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4, !alias.scope [[META20:![0-9]+]], !noalias [[META23:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !alias.scope [[META20]], !noalias [[META23]] ; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP5]], align 4, !alias.scope [[META23]] ; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP6]], align 4, !alias.scope [[META23]] ; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = add nsw i32 [[TMP3]], 23 ; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP4]], 23 ; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = icmp slt i32 [[TMP3]], 100 ; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP4]], 100 ; UNROLL-NO-VF-NEXT: br i1 [[TMP11]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]] ; UNROLL-NO-VF: [[PRED_SDIV_IF]]: ; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = sdiv i32 [[TMP9]], [[TMP3]] ; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = sdiv i32 [[TMP7]], [[TMP13]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_SDIV_CONTINUE]] ; UNROLL-NO-VF: [[PRED_SDIV_CONTINUE]]: ; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP14]], %[[PRED_SDIV_IF]] ] ; UNROLL-NO-VF-NEXT: br i1 [[TMP12]], label %[[PRED_SDIV_IF2:.*]], label %[[PRED_SDIV_CONTINUE3]] ; UNROLL-NO-VF: [[PRED_SDIV_IF2]]: ; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = sdiv i32 [[TMP10]], [[TMP4]] ; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = sdiv i32 [[TMP8]], [[TMP16]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_SDIV_CONTINUE3]] ; UNROLL-NO-VF: [[PRED_SDIV_CONTINUE3]]: ; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = phi i32 [ poison, %[[PRED_SDIV_CONTINUE]] ], [ [[TMP17]], %[[PRED_SDIV_IF2]] ] ; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP11]], i32 [[TMP15]], i32 [[TMP9]] ; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[TMP12]], i32 [[TMP18]], i32 [[TMP10]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI]], ptr [[TMP1]], align 4, !alias.scope [[META20]], !noalias [[META23]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI4]], ptr [[TMP2]], align 4, !alias.scope [[META20]], !noalias [[META23]] ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 ; UNROLL-NO-VF-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP25:![0-9]+]] ; UNROLL-NO-VF: [[MIDDLE_BLOCK]]: ; UNROLL-NO-VF-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; UNROLL-NO-VF: [[SCALAR_PH]]: ; UNROLL-NO-VF-NEXT: br label %[[FOR_BODY:.*]] ; UNROLL-NO-VF: [[FOR_COND_CLEANUP]]: ; UNROLL-NO-VF-NEXT: ret void ; UNROLL-NO-VF: [[FOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[IF_END:.*]] ] ; UNROLL-NO-VF-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4 ; UNROLL-NO-VF-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4 ; UNROLL-NO-VF-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23 ; UNROLL-NO-VF-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100 ; UNROLL-NO-VF-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[IF_END]] ; UNROLL-NO-VF: [[IF_THEN]]: ; UNROLL-NO-VF-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]] ; UNROLL-NO-VF-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]] ; UNROLL-NO-VF-NEXT: br label %[[IF_END]] ; UNROLL-NO-VF: [[IF_END]]: ; UNROLL-NO-VF-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], %[[IF_THEN]] ], [ [[PSD]], %[[FOR_BODY]] ] ; UNROLL-NO-VF-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4 ; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128 ; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]] ; entry: br label %for.body for.cond.cleanup: ret void for.body: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ] %isd = getelementptr inbounds i32, ptr %asd, i64 %indvars.iv %lsd = load i32, ptr %isd, align 4 %isd.b = getelementptr inbounds i32, ptr %bsd, i64 %indvars.iv %lsd.b = load i32, ptr %isd.b, align 4 %psd = add nsw i32 %lsd, 23 %cmp1 = icmp slt i32 %lsd, 100 br i1 %cmp1, label %if.then, label %if.end if.then: %sd1 = sdiv i32 %psd, %lsd %rsd = sdiv i32 %lsd.b, %sd1 br label %if.end if.end: %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ] store i32 %ysd.0, ptr %isd, align 4 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 128 br i1 %exitcond, label %for.cond.cleanup, label %for.body } define void @pr30172(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {; ; CHECK-LABEL: define void @pr30172( ; CHECK-SAME: ptr captures(none) [[ASD:%.*]], ptr captures(none) [[BSD:%.*]]) !dbg [[DBG27:![0-9]+]] { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD]], i64 512 ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD]], i64 512 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE4:.*]] ] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP0]], align 4, !alias.scope [[META29:![0-9]+]], !noalias [[META32:![0-9]+]] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4, !alias.scope [[META32]] ; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], splat (i32 23) ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], splat (i32 100) ; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i1> [[TMP3]], splat (i1 true), !dbg [[DBG34:![0-9]+]] ; CHECK-NEXT: [[TMP5:%.*]] = icmp sge <2 x i32> [[WIDE_LOAD]], splat (i32 200) ; CHECK-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP4]], <2 x i1> [[TMP5]], <2 x i1> zeroinitializer, !dbg [[DBG35:![0-9]+]] ; CHECK-NEXT: [[TMP7:%.*]] = or <2 x i1> [[TMP6]], [[TMP3]] ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i64 0 ; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]] ; CHECK: [[PRED_SDIV_IF]]: ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0 ; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 0 ; CHECK-NEXT: [[TMP11:%.*]] = sdiv i32 [[TMP9]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i64 0 ; CHECK-NEXT: [[TMP13:%.*]] = sdiv i32 [[TMP12]], [[TMP11]] ; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i32> poison, i32 [[TMP13]], i64 0 ; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]] ; CHECK: [[PRED_SDIV_CONTINUE]]: ; CHECK-NEXT: [[TMP15:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP14]], %[[PRED_SDIV_IF]] ] ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i1> [[TMP7]], i64 1 ; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_SDIV_IF3:.*]], label %[[PRED_SDIV_CONTINUE4]] ; CHECK: [[PRED_SDIV_IF3]]: ; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1 ; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 1 ; CHECK-NEXT: [[TMP19:%.*]] = sdiv i32 [[TMP17]], [[TMP18]] ; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i32> [[WIDE_LOAD2]], i64 1 ; CHECK-NEXT: [[TMP21:%.*]] = sdiv i32 [[TMP20]], [[TMP19]] ; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x i32> [[TMP15]], i32 [[TMP21]], i64 1 ; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE4]] ; CHECK: [[PRED_SDIV_CONTINUE4]]: ; CHECK-NEXT: [[TMP23:%.*]] = phi <2 x i32> [ [[TMP15]], %[[PRED_SDIV_CONTINUE]] ], [ [[TMP22]], %[[PRED_SDIV_IF3]] ] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP7]], <2 x i32> [[TMP23]], <2 x i32> [[TMP2]] ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP0]], align 4, !alias.scope [[META29]], !noalias [[META32]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 ; CHECK-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: br label %[[FOR_BODY:.*]] ; CHECK: [[FOR_COND_CLEANUP]]: ; CHECK-NEXT: ret void ; CHECK: [[FOR_BODY]]: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[IF_END:.*]] ] ; CHECK-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4 ; CHECK-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4 ; CHECK-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100 ; CHECK-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[CHECKBB:.*]], !dbg [[DBG34]] ; CHECK: [[CHECKBB]]: ; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[LSD]], 200 ; CHECK-NEXT: br i1 [[CMP2]], label %[[IF_THEN]], label %[[IF_END]], !dbg [[DBG35]] ; CHECK: [[IF_THEN]]: ; CHECK-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]] ; CHECK-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]] ; CHECK-NEXT: br label %[[IF_END]] ; CHECK: [[IF_END]]: ; CHECK-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], %[[IF_THEN]] ], [ [[PSD]], %[[CHECKBB]] ] ; CHECK-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128 ; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP37:![0-9]+]] ; ; UNROLL-NO-VF-LABEL: define void @pr30172( ; UNROLL-NO-VF-SAME: ptr captures(none) [[ASD:%.*]], ptr captures(none) [[BSD:%.*]]) !dbg [[DBG27:![0-9]+]] { ; UNROLL-NO-VF-NEXT: [[ENTRY:.*:]] ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; UNROLL-NO-VF: [[VECTOR_MEMCHECK]]: ; UNROLL-NO-VF-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ASD]], i64 512 ; UNROLL-NO-VF-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[BSD]], i64 512 ; UNROLL-NO-VF-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[ASD]], [[SCEVGEP1]] ; UNROLL-NO-VF-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BSD]], [[SCEVGEP]] ; UNROLL-NO-VF-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; UNROLL-NO-VF-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; UNROLL-NO-VF: [[VECTOR_PH]]: ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_BODY:.*]] ; UNROLL-NO-VF: [[VECTOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE3:.*]] ] ; UNROLL-NO-VF-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4, !alias.scope [[META29:![0-9]+]], !noalias [[META32:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !alias.scope [[META29]], !noalias [[META32]] ; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP5]], align 4, !alias.scope [[META32]] ; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP6]], align 4, !alias.scope [[META32]] ; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = add nsw i32 [[TMP3]], 23 ; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP4]], 23 ; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = icmp slt i32 [[TMP3]], 100 ; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP4]], 100 ; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = xor i1 [[TMP11]], true, !dbg [[DBG34:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = xor i1 [[TMP12]], true, !dbg [[DBG34]] ; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP3]], 200 ; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP4]], 200 ; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = select i1 [[TMP13]], i1 [[TMP15]], i1 false, !dbg [[DBG35:![0-9]+]] ; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = select i1 [[TMP14]], i1 [[TMP16]], i1 false, !dbg [[DBG35]] ; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = or i1 [[TMP17]], [[TMP11]] ; UNROLL-NO-VF-NEXT: [[TMP20:%.*]] = or i1 [[TMP18]], [[TMP12]] ; UNROLL-NO-VF-NEXT: br i1 [[TMP19]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]] ; UNROLL-NO-VF: [[PRED_SDIV_IF]]: ; UNROLL-NO-VF-NEXT: [[TMP21:%.*]] = sdiv i32 [[TMP9]], [[TMP3]] ; UNROLL-NO-VF-NEXT: [[TMP22:%.*]] = sdiv i32 [[TMP7]], [[TMP21]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_SDIV_CONTINUE]] ; UNROLL-NO-VF: [[PRED_SDIV_CONTINUE]]: ; UNROLL-NO-VF-NEXT: [[TMP23:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP22]], %[[PRED_SDIV_IF]] ] ; UNROLL-NO-VF-NEXT: br i1 [[TMP20]], label %[[PRED_SDIV_IF2:.*]], label %[[PRED_SDIV_CONTINUE3]] ; UNROLL-NO-VF: [[PRED_SDIV_IF2]]: ; UNROLL-NO-VF-NEXT: [[TMP24:%.*]] = sdiv i32 [[TMP10]], [[TMP4]] ; UNROLL-NO-VF-NEXT: [[TMP25:%.*]] = sdiv i32 [[TMP8]], [[TMP24]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_SDIV_CONTINUE3]] ; UNROLL-NO-VF: [[PRED_SDIV_CONTINUE3]]: ; UNROLL-NO-VF-NEXT: [[TMP26:%.*]] = phi i32 [ poison, %[[PRED_SDIV_CONTINUE]] ], [ [[TMP25]], %[[PRED_SDIV_IF2]] ] ; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP19]], i32 [[TMP23]], i32 [[TMP9]] ; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[TMP20]], i32 [[TMP26]], i32 [[TMP10]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI]], ptr [[TMP1]], align 4, !alias.scope [[META29]], !noalias [[META32]] ; UNROLL-NO-VF-NEXT: store i32 [[PREDPHI4]], ptr [[TMP2]], align 4, !alias.scope [[META29]], !noalias [[META32]] ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 ; UNROLL-NO-VF-NEXT: br i1 [[TMP27]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]] ; UNROLL-NO-VF: [[MIDDLE_BLOCK]]: ; UNROLL-NO-VF-NEXT: br label %[[FOR_COND_CLEANUP:.*]] ; UNROLL-NO-VF: [[SCALAR_PH]]: ; UNROLL-NO-VF-NEXT: br label %[[FOR_BODY:.*]] ; UNROLL-NO-VF: [[FOR_COND_CLEANUP]]: ; UNROLL-NO-VF-NEXT: ret void ; UNROLL-NO-VF: [[FOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[IF_END:.*]] ] ; UNROLL-NO-VF-NEXT: [[ISD:%.*]] = getelementptr inbounds i32, ptr [[ASD]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[LSD:%.*]] = load i32, ptr [[ISD]], align 4 ; UNROLL-NO-VF-NEXT: [[ISD_B:%.*]] = getelementptr inbounds i32, ptr [[BSD]], i64 [[INDVARS_IV]] ; UNROLL-NO-VF-NEXT: [[LSD_B:%.*]] = load i32, ptr [[ISD_B]], align 4 ; UNROLL-NO-VF-NEXT: [[PSD:%.*]] = add nsw i32 [[LSD]], 23 ; UNROLL-NO-VF-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100 ; UNROLL-NO-VF-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[CHECKBB:.*]], !dbg [[DBG34]] ; UNROLL-NO-VF: [[CHECKBB]]: ; UNROLL-NO-VF-NEXT: [[CMP2:%.*]] = icmp sge i32 [[LSD]], 200 ; UNROLL-NO-VF-NEXT: br i1 [[CMP2]], label %[[IF_THEN]], label %[[IF_END]], !dbg [[DBG35]] ; UNROLL-NO-VF: [[IF_THEN]]: ; UNROLL-NO-VF-NEXT: [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]] ; UNROLL-NO-VF-NEXT: [[RSD:%.*]] = sdiv i32 [[LSD_B]], [[SD1]] ; UNROLL-NO-VF-NEXT: br label %[[IF_END]] ; UNROLL-NO-VF: [[IF_END]]: ; UNROLL-NO-VF-NEXT: [[YSD_0:%.*]] = phi i32 [ [[RSD]], %[[IF_THEN]] ], [ [[PSD]], %[[CHECKBB]] ] ; UNROLL-NO-VF-NEXT: store i32 [[YSD_0]], ptr [[ISD]], align 4 ; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128 ; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP37:![0-9]+]] ; entry: br label %for.body for.cond.cleanup: ret void for.body: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ] %isd = getelementptr inbounds i32, ptr %asd, i64 %indvars.iv %lsd = load i32, ptr %isd, align 4 %isd.b = getelementptr inbounds i32, ptr %bsd, i64 %indvars.iv %lsd.b = load i32, ptr %isd.b, align 4 %psd = add nsw i32 %lsd, 23 %cmp1 = icmp slt i32 %lsd, 100 br i1 %cmp1, label %if.then, label %checkbb, !dbg !7 checkbb: %cmp2 = icmp sge i32 %lsd, 200 br i1 %cmp2, label %if.then, label %if.end, !dbg !8 if.then: %sd1 = sdiv i32 %psd, %lsd %rsd = sdiv i32 %lsd.b, %sd1 br label %if.end if.end: %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %checkbb ] store i32 %ysd.0, ptr %isd, align 4 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 128 br i1 %exitcond, label %for.cond.cleanup, label %for.body } define i32 @predicated_udiv_scalarized_operand(ptr %a, i1 %c, i32 %x, i64 %n) { ; CHECK-LABEL: define i32 @predicated_udiv_scalarized_operand( ; CHECK-SAME: ptr [[A:%.*]], i1 [[C:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) { ; CHECK-NEXT: [[ENTRY:.*]]: ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1) ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 2 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[SMAX]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[SMAX]], [[N_MOD_VF]] ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_UDIV_CONTINUE2:.*]] ] ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[PRED_UDIV_CONTINUE2]] ] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP0]], align 4 ; CHECK-NEXT: br i1 [[C]], label %[[PRED_UDIV_IF:.*]], label %[[PRED_UDIV_CONTINUE:.*]] ; CHECK: [[PRED_UDIV_IF]]: ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 0 ; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], [[X]] ; CHECK-NEXT: [[TMP4:%.*]] = udiv i32 [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i64 0 ; CHECK-NEXT: br label %[[PRED_UDIV_CONTINUE]] ; CHECK: [[PRED_UDIV_CONTINUE]]: ; CHECK-NEXT: [[TMP6:%.*]] = phi <2 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP5]], %[[PRED_UDIV_IF]] ] ; CHECK-NEXT: br i1 [[C]], label %[[PRED_UDIV_IF1:.*]], label %[[PRED_UDIV_CONTINUE2]] ; CHECK: [[PRED_UDIV_IF1]]: ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i64 1 ; CHECK-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP7]], [[X]] ; CHECK-NEXT: [[TMP10:%.*]] = udiv i32 [[TMP7]], [[TMP8]] ; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP10]], i64 1 ; CHECK-NEXT: br label %[[PRED_UDIV_CONTINUE2]] ; CHECK: [[PRED_UDIV_CONTINUE2]]: ; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i32> [ [[TMP6]], %[[PRED_UDIV_CONTINUE]] ], [ [[TMP11]], %[[PRED_UDIV_IF1]] ] ; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <2 x i32> [[TMP12]], <2 x i32> [[WIDE_LOAD]] ; CHECK-NEXT: [[TMP13]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP38:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP13]]) ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP15]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-NEXT: br label %[[FOR_BODY:.*]] ; CHECK: [[FOR_BODY]]: ; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_INC:.*]] ] ; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[T6:%.*]], %[[FOR_INC]] ] ; CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]] ; CHECK-NEXT: [[T2:%.*]] = load i32, ptr [[T0]], align 4 ; CHECK-NEXT: br i1 [[C]], label %[[IF_THEN:.*]], label %[[FOR_INC]] ; CHECK: [[IF_THEN]]: ; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], [[X]] ; CHECK-NEXT: [[T4:%.*]] = udiv i32 [[T2]], [[T3]] ; CHECK-NEXT: br label %[[FOR_INC]] ; CHECK: [[FOR_INC]]: ; CHECK-NEXT: [[T5:%.*]] = phi i32 [ [[T2]], %[[FOR_BODY]] ], [ [[T4]], %[[IF_THEN]] ] ; CHECK-NEXT: [[T6]] = add i32 [[R]], [[T5]] ; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]] ; CHECK-NEXT: br i1 [[COND]], label %[[FOR_BODY]], label %[[FOR_END]], !llvm.loop [[LOOP39:![0-9]+]] ; CHECK: [[FOR_END]]: ; CHECK-NEXT: [[T7:%.*]] = phi i32 [ [[T6]], %[[FOR_INC]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[T7]] ; ; UNROLL-NO-VF-LABEL: define i32 @predicated_udiv_scalarized_operand( ; UNROLL-NO-VF-SAME: ptr [[A:%.*]], i1 [[C:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) { ; UNROLL-NO-VF-NEXT: [[ENTRY:.*]]: ; UNROLL-NO-VF-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1) ; UNROLL-NO-VF-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 2 ; UNROLL-NO-VF-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; UNROLL-NO-VF: [[VECTOR_PH]]: ; UNROLL-NO-VF-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[SMAX]], 2 ; UNROLL-NO-VF-NEXT: [[N_VEC:%.*]] = sub i64 [[SMAX]], [[N_MOD_VF]] ; UNROLL-NO-VF-NEXT: br label %[[VECTOR_BODY:.*]] ; UNROLL-NO-VF: [[VECTOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_UDIV_CONTINUE3:.*]] ] ; UNROLL-NO-VF-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[PRED_UDIV_CONTINUE3]] ] ; UNROLL-NO-VF-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[PRED_UDIV_CONTINUE3]] ] ; UNROLL-NO-VF-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 ; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] ; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP0]] ; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4 ; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4 ; UNROLL-NO-VF-NEXT: br i1 [[C]], label %[[PRED_UDIV_IF:.*]], label %[[PRED_UDIV_CONTINUE:.*]] ; UNROLL-NO-VF: [[PRED_UDIV_IF]]: ; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = add nsw i32 [[TMP3]], [[X]] ; UNROLL-NO-VF-NEXT: [[TMP6:%.*]] = udiv i32 [[TMP3]], [[TMP5]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_UDIV_CONTINUE]] ; UNROLL-NO-VF: [[PRED_UDIV_CONTINUE]]: ; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = phi i32 [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_UDIV_IF]] ] ; UNROLL-NO-VF-NEXT: br i1 [[C]], label %[[PRED_UDIV_IF2:.*]], label %[[PRED_UDIV_CONTINUE3]] ; UNROLL-NO-VF: [[PRED_UDIV_IF2]]: ; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP4]], [[X]] ; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = udiv i32 [[TMP4]], [[TMP8]] ; UNROLL-NO-VF-NEXT: br label %[[PRED_UDIV_CONTINUE3]] ; UNROLL-NO-VF: [[PRED_UDIV_CONTINUE3]]: ; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = phi i32 [ poison, %[[PRED_UDIV_CONTINUE]] ], [ [[TMP9]], %[[PRED_UDIV_IF2]] ] ; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], i32 [[TMP7]], i32 [[TMP3]] ; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[C]], i32 [[TMP10]], i32 [[TMP4]] ; UNROLL-NO-VF-NEXT: [[TMP11]] = add i32 [[VEC_PHI]], [[PREDPHI]] ; UNROLL-NO-VF-NEXT: [[TMP12]] = add i32 [[VEC_PHI1]], [[PREDPHI4]] ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP38:![0-9]+]] ; UNROLL-NO-VF: [[MIDDLE_BLOCK]]: ; UNROLL-NO-VF-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP12]], [[TMP11]] ; UNROLL-NO-VF-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]] ; UNROLL-NO-VF: [[SCALAR_PH]]: ; UNROLL-NO-VF-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; UNROLL-NO-VF-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; UNROLL-NO-VF-NEXT: br label %[[FOR_BODY:.*]] ; UNROLL-NO-VF: [[FOR_BODY]]: ; UNROLL-NO-VF-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_INC:.*]] ] ; UNROLL-NO-VF-NEXT: [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[T6:%.*]], %[[FOR_INC]] ] ; UNROLL-NO-VF-NEXT: [[T0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]] ; UNROLL-NO-VF-NEXT: [[T2:%.*]] = load i32, ptr [[T0]], align 4 ; UNROLL-NO-VF-NEXT: br i1 [[C]], label %[[IF_THEN:.*]], label %[[FOR_INC]] ; UNROLL-NO-VF: [[IF_THEN]]: ; UNROLL-NO-VF-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], [[X]] ; UNROLL-NO-VF-NEXT: [[T4:%.*]] = udiv i32 [[T2]], [[T3]] ; UNROLL-NO-VF-NEXT: br label %[[FOR_INC]] ; UNROLL-NO-VF: [[FOR_INC]]: ; UNROLL-NO-VF-NEXT: [[T5:%.*]] = phi i32 [ [[T2]], %[[FOR_BODY]] ], [ [[T4]], %[[IF_THEN]] ] ; UNROLL-NO-VF-NEXT: [[T6]] = add i32 [[R]], [[T5]] ; UNROLL-NO-VF-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 ; UNROLL-NO-VF-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]] ; UNROLL-NO-VF-NEXT: br i1 [[COND]], label %[[FOR_BODY]], label %[[FOR_END]], !llvm.loop [[LOOP39:![0-9]+]] ; UNROLL-NO-VF: [[FOR_END]]: ; UNROLL-NO-VF-NEXT: [[T7:%.*]] = phi i32 [ [[T6]], %[[FOR_INC]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ] ; UNROLL-NO-VF-NEXT: ret i32 [[T7]] ; entry: br label %for.body ; Test predicating an instruction that feeds a vectorizable use, when unrolled ; but not vectorized. Derived from pr34248 reproducer. for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ] %r = phi i32 [ 0, %entry ], [ %t6, %for.inc ] %t0 = getelementptr inbounds i32, ptr %a, i64 %i %t2 = load i32, ptr %t0, align 4 br i1 %c, label %if.then, label %for.inc if.then: %t3 = add nsw i32 %t2, %x %t4 = udiv i32 %t2, %t3 br label %for.inc for.inc: %t5 = phi i32 [ %t2, %for.body ], [ %t4, %if.then] %t6 = add i32 %r, %t5 %i.next = add nuw nsw i64 %i, 1 %cond = icmp slt i64 %i.next, %n br i1 %cond, label %for.body, label %for.end for.end: %t7 = phi i32 [ %t6, %for.inc ] ret i32 %t7 } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4} !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2) !1 = !DIFile(filename: "/tmp/s.c", directory: "/tmp") !2 = !{} !3 = !{i32 2, !"Debug Info Version", i32 3} !4 = !{i32 7, !"PIC Level", i32 2} !5 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 4, type: !6, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2) !6 = !DISubroutineType(types: !2) !7 = !DILocation(line: 5, column: 21, scope: !5) !8 = !DILocation(line: 5, column: 3, scope: !5)