# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -mattr='+xsfvfnrclipxfqf' -iterations=1 -instruction-tables=full %s | \ # RUN: FileCheck %s vsetvli a0, zero, e8, mf8, ta, ma sf.vfnrclip.xu.f.qf v4, v8, fa2 vsetvli a0, zero, e8, mf4, ta, ma sf.vfnrclip.xu.f.qf v4, v8, fa2 vsetvli a0, zero, e8, mf2, ta, ma sf.vfnrclip.xu.f.qf v4, v8, fa2 vsetvli a0, zero, e8, m1, ta, ma sf.vfnrclip.xu.f.qf v4, v8, fa2 vsetvli a0, zero, e8, m2, ta, ma sf.vfnrclip.xu.f.qf v4, v8, fa2 # CHECK: Resources: # CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv:1 # CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv:1 # CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA:1 # CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB # CHECK-NEXT: [4] - VLEN1024X300SiFive7PipeB:1 # CHECK-NEXT: [5] - VLEN1024X300SiFive7VA1:1 # CHECK-NEXT: [6] - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2 # CHECK-NEXT: [7] - VLEN1024X300SiFive7VA2:1 # CHECK-NEXT: [8] - VLEN1024X300SiFive7VCQ:1 # CHECK-NEXT: [9] - VLEN1024X300SiFive7VL:1 # CHECK-NEXT: [10] - VLEN1024X300SiFive7VS:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [7]: Bypass Latency # CHECK-NEXT: [8]: Resources ( | [] | [,