Architectures: gfx90a: Capabilities: ArchAccUnifiedRegs: 0 CMPXWritesSGPR: 0 DefaultWavefrontSize: 64 HasAccCD: 0 HasAccumOffset: 0 HasAddLshl: 0 HasAtomicAdd: 0 HasCodeObjectV4: 0 HasCodeObjectV5: 0 HasDirectToLds: 0 HasExpcnt: 0 HasExplicitVectorCO: 0 HasExplicitVectorRevCO: 0 HasGlobalOffset: 0 HasLshlOr: 0 HasMFMA: 0 HasMFMA_bf16_16x16x16_1k: 0 HasMFMA_bf16_32x32x4: 0 HasMFMA_bf16_32x32x4_1k: 0 HasMFMA_f64: 0 HasSMulHi: 0 HasWave64: 0 MaxExpcnt: 7 MaxLdsSize: 65536 MaxLgkmcnt: 15 MaxVmcnt: 63 MaxPreloadedKernargs: 16 PackedWorkitemIDs: 0 SupportedISA: 0 SupportedSource: 0 Waitcnt0Disabled: 0 s_barrier: 0 v_add3_u32: 0 v_dot2_f32_f16: 0 v_dot2c_f32_f16: 0 v_dot4c_i32_i8: 0 v_fma_f16: 0 v_fma_f32: 0 v_fma_mix_f32: 0 v_fmac_f32: 0 v_mac_f16: 0 v_mac_f32: 0 v_pk_fma_f16: 0 ISAVersion: ArchString: gfx90a AsicRevisionId: -1 Sramecc: false Xnack: false InstructionInfos: buffer_atomic_add: ImplicitAccess: false Instruction: buffer_atomic_add IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_add_f32: ImplicitAccess: false Instruction: buffer_atomic_add_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_add_f64: ImplicitAccess: false Instruction: buffer_atomic_add_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_add_x2: ImplicitAccess: false Instruction: buffer_atomic_add_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_and: ImplicitAccess: false Instruction: buffer_atomic_and IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_and_x2: ImplicitAccess: false Instruction: buffer_atomic_and_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_cmpswap: ImplicitAccess: false Instruction: buffer_atomic_cmpswap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_cmpswap_x2: ImplicitAccess: false Instruction: buffer_atomic_cmpswap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_dec: ImplicitAccess: false Instruction: buffer_atomic_dec IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_dec_x2: ImplicitAccess: false Instruction: buffer_atomic_dec_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_inc: ImplicitAccess: false Instruction: buffer_atomic_inc IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_inc_x2: ImplicitAccess: false Instruction: buffer_atomic_inc_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_max_f64: ImplicitAccess: false Instruction: buffer_atomic_max_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_min_f64: ImplicitAccess: false Instruction: buffer_atomic_min_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_or: ImplicitAccess: false Instruction: buffer_atomic_or IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_or_x2: ImplicitAccess: false Instruction: buffer_atomic_or_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_pk_add_f16: ImplicitAccess: false Instruction: buffer_atomic_pk_add_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_smax: ImplicitAccess: false Instruction: buffer_atomic_smax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_smax_x2: ImplicitAccess: false Instruction: buffer_atomic_smax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_smin: ImplicitAccess: false Instruction: buffer_atomic_smin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_smin_x2: ImplicitAccess: false Instruction: buffer_atomic_smin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_sub: ImplicitAccess: false Instruction: buffer_atomic_sub IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_sub_x2: ImplicitAccess: false Instruction: buffer_atomic_sub_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_swap: ImplicitAccess: false Instruction: buffer_atomic_swap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_swap_x2: ImplicitAccess: false Instruction: buffer_atomic_swap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_umax: ImplicitAccess: false Instruction: buffer_atomic_umax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_umax_x2: ImplicitAccess: false Instruction: buffer_atomic_umax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_umin: ImplicitAccess: false Instruction: buffer_atomic_umin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_umin_x2: ImplicitAccess: false Instruction: buffer_atomic_umin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_xor: ImplicitAccess: false Instruction: buffer_atomic_xor IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_atomic_xor_x2: ImplicitAccess: false Instruction: buffer_atomic_xor_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_invl2: ImplicitAccess: false Instruction: buffer_invl2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_dword: ImplicitAccess: false Instruction: buffer_load_dword IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_dwordx2: ImplicitAccess: false Instruction: buffer_load_dwordx2 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_dwordx3: ImplicitAccess: false Instruction: buffer_load_dwordx3 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_dwordx4: ImplicitAccess: false Instruction: buffer_load_dwordx4 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_format_d16_hi_x: ImplicitAccess: false Instruction: buffer_load_format_d16_hi_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_d16_x: ImplicitAccess: false Instruction: buffer_load_format_d16_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_d16_xy: ImplicitAccess: false Instruction: buffer_load_format_d16_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_d16_xyz: ImplicitAccess: false Instruction: buffer_load_format_d16_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_d16_xyzw: ImplicitAccess: false Instruction: buffer_load_format_d16_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_x: ImplicitAccess: false Instruction: buffer_load_format_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_xy: ImplicitAccess: false Instruction: buffer_load_format_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_xyz: ImplicitAccess: false Instruction: buffer_load_format_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_format_xyzw: ImplicitAccess: false Instruction: buffer_load_format_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_load_sbyte: ImplicitAccess: false Instruction: buffer_load_sbyte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_sbyte_d16: ImplicitAccess: false Instruction: buffer_load_sbyte_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_sbyte_d16_hi: ImplicitAccess: false Instruction: buffer_load_sbyte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_short_d16: ImplicitAccess: false Instruction: buffer_load_short_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_short_d16_hi: ImplicitAccess: false Instruction: buffer_load_short_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_sshort: ImplicitAccess: false Instruction: buffer_load_sshort IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_ubyte: ImplicitAccess: false Instruction: buffer_load_ubyte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_ubyte_d16: ImplicitAccess: false Instruction: buffer_load_ubyte_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_ubyte_d16_hi: ImplicitAccess: false Instruction: buffer_load_ubyte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_load_ushort: ImplicitAccess: false Instruction: buffer_load_ushort IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - LoadQueue buffer_store_byte: ImplicitAccess: false Instruction: buffer_store_byte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_byte_d16_hi: ImplicitAccess: false Instruction: buffer_store_byte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_dword: ImplicitAccess: false Instruction: buffer_store_dword IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_dwordx2: ImplicitAccess: false Instruction: buffer_store_dwordx2 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_dwordx3: ImplicitAccess: false Instruction: buffer_store_dwordx3 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_dwordx4: ImplicitAccess: false Instruction: buffer_store_dwordx4 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_format_d16_hi_x: ImplicitAccess: false Instruction: buffer_store_format_d16_hi_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_d16_x: ImplicitAccess: false Instruction: buffer_store_format_d16_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_d16_xy: ImplicitAccess: false Instruction: buffer_store_format_d16_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_d16_xyz: ImplicitAccess: false Instruction: buffer_store_format_d16_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_d16_xyzw: ImplicitAccess: false Instruction: buffer_store_format_d16_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_x: ImplicitAccess: false Instruction: buffer_store_format_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_xy: ImplicitAccess: false Instruction: buffer_store_format_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_xyz: ImplicitAccess: false Instruction: buffer_store_format_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_format_xyzw: ImplicitAccess: false Instruction: buffer_store_format_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_lds_dword: ImplicitAccess: false Instruction: buffer_store_lds_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_store_short: ImplicitAccess: false Instruction: buffer_store_short IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_store_short_d16_hi: ImplicitAccess: false Instruction: buffer_store_short_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 1 WaitQueues: - StoreQueue buffer_wbinvl1: ImplicitAccess: false Instruction: buffer_wbinvl1 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_wbinvl1_vol: ImplicitAccess: false Instruction: buffer_wbinvl1_vol IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] buffer_wbl2: ImplicitAccess: false Instruction: buffer_wbl2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_f32: ImplicitAccess: false Instruction: ds_add_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_f64: ImplicitAccess: false Instruction: ds_add_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_rtn_f32: ImplicitAccess: false Instruction: ds_add_rtn_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_rtn_f64: ImplicitAccess: false Instruction: ds_add_rtn_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_rtn_u32: ImplicitAccess: false Instruction: ds_add_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_rtn_u64: ImplicitAccess: false Instruction: ds_add_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_u32: ImplicitAccess: false Instruction: ds_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_add_u64: ImplicitAccess: false Instruction: ds_add_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_and_b32: ImplicitAccess: false Instruction: ds_and_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_and_b64: ImplicitAccess: false Instruction: ds_and_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_and_rtn_b32: ImplicitAccess: false Instruction: ds_and_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_and_rtn_b64: ImplicitAccess: false Instruction: ds_and_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_append: ImplicitAccess: false Instruction: ds_append IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_bpermute_b32: ImplicitAccess: false Instruction: ds_bpermute_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_b32: ImplicitAccess: false Instruction: ds_cmpst_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_b64: ImplicitAccess: false Instruction: ds_cmpst_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_f32: ImplicitAccess: false Instruction: ds_cmpst_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_f64: ImplicitAccess: false Instruction: ds_cmpst_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_rtn_b32: ImplicitAccess: false Instruction: ds_cmpst_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_rtn_b64: ImplicitAccess: false Instruction: ds_cmpst_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_rtn_f32: ImplicitAccess: false Instruction: ds_cmpst_rtn_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_cmpst_rtn_f64: ImplicitAccess: false Instruction: ds_cmpst_rtn_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_condxchg32_rtn_b64: ImplicitAccess: false Instruction: ds_condxchg32_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_consume: ImplicitAccess: false Instruction: ds_consume IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_dec_rtn_u32: ImplicitAccess: false Instruction: ds_dec_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_dec_rtn_u64: ImplicitAccess: false Instruction: ds_dec_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_dec_u32: ImplicitAccess: false Instruction: ds_dec_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_dec_u64: ImplicitAccess: false Instruction: ds_dec_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_gws_barrier: ImplicitAccess: false Instruction: ds_gws_barrier IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_gws_init: ImplicitAccess: false Instruction: ds_gws_init IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_gws_sema_br: ImplicitAccess: false Instruction: ds_gws_sema_br IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_gws_sema_p: ImplicitAccess: false Instruction: ds_gws_sema_p IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_gws_sema_release_all: ImplicitAccess: false Instruction: ds_gws_sema_release_all IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_gws_sema_v: ImplicitAccess: false Instruction: ds_gws_sema_v IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_inc_rtn_u32: ImplicitAccess: false Instruction: ds_inc_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_inc_rtn_u64: ImplicitAccess: false Instruction: ds_inc_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_inc_u32: ImplicitAccess: false Instruction: ds_inc_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_inc_u64: ImplicitAccess: false Instruction: ds_inc_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_f32: ImplicitAccess: false Instruction: ds_max_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_f64: ImplicitAccess: false Instruction: ds_max_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_i32: ImplicitAccess: false Instruction: ds_max_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_i64: ImplicitAccess: false Instruction: ds_max_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_rtn_f32: ImplicitAccess: false Instruction: ds_max_rtn_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_rtn_f64: ImplicitAccess: false Instruction: ds_max_rtn_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_rtn_i32: ImplicitAccess: false Instruction: ds_max_rtn_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_rtn_i64: ImplicitAccess: false Instruction: ds_max_rtn_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_rtn_u32: ImplicitAccess: false Instruction: ds_max_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_rtn_u64: ImplicitAccess: false Instruction: ds_max_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_u32: ImplicitAccess: false Instruction: ds_max_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_max_u64: ImplicitAccess: false Instruction: ds_max_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_f32: ImplicitAccess: false Instruction: ds_min_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_f64: ImplicitAccess: false Instruction: ds_min_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_i32: ImplicitAccess: false Instruction: ds_min_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_i64: ImplicitAccess: false Instruction: ds_min_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_rtn_f32: ImplicitAccess: false Instruction: ds_min_rtn_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_rtn_f64: ImplicitAccess: false Instruction: ds_min_rtn_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_rtn_i32: ImplicitAccess: false Instruction: ds_min_rtn_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_rtn_i64: ImplicitAccess: false Instruction: ds_min_rtn_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_rtn_u32: ImplicitAccess: false Instruction: ds_min_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_rtn_u64: ImplicitAccess: false Instruction: ds_min_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_u32: ImplicitAccess: false Instruction: ds_min_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_min_u64: ImplicitAccess: false Instruction: ds_min_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_mskor_b32: ImplicitAccess: false Instruction: ds_mskor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_mskor_b64: ImplicitAccess: false Instruction: ds_mskor_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_mskor_rtn_b32: ImplicitAccess: false Instruction: ds_mskor_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_mskor_rtn_b64: ImplicitAccess: false Instruction: ds_mskor_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_nop: ImplicitAccess: false Instruction: ds_nop IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_or_b32: ImplicitAccess: false Instruction: ds_or_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_or_b64: ImplicitAccess: false Instruction: ds_or_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_or_rtn_b32: ImplicitAccess: false Instruction: ds_or_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_or_rtn_b64: ImplicitAccess: false Instruction: ds_or_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_permute_b32: ImplicitAccess: false Instruction: ds_permute_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_read2_b32: ImplicitAccess: false Instruction: ds_read2_b32 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_read2_b64: ImplicitAccess: false Instruction: ds_read2_b64 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_read2st64_b32: ImplicitAccess: false Instruction: ds_read2st64_b32 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_read2st64_b64: ImplicitAccess: false Instruction: ds_read2st64_b64 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_read_addtid_b32: ImplicitAccess: false Instruction: ds_read_addtid_b32 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_b128: ImplicitAccess: false Instruction: ds_read_b128 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_b32: ImplicitAccess: false Instruction: ds_read_b32 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_b64: ImplicitAccess: false Instruction: ds_read_b64 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_b96: ImplicitAccess: false Instruction: ds_read_b96 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_i16: ImplicitAccess: false Instruction: ds_read_i16 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_i8: ImplicitAccess: false Instruction: ds_read_i8 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_i8_d16: ImplicitAccess: false Instruction: ds_read_i8_d16 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_i8_d16_hi: ImplicitAccess: false Instruction: ds_read_i8_d16_hi IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_u16: ImplicitAccess: false Instruction: ds_read_u16 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_u16_d16: ImplicitAccess: false Instruction: ds_read_u16_d16 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_u16_d16_hi: ImplicitAccess: false Instruction: ds_read_u16_d16_hi IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_u8: ImplicitAccess: false Instruction: ds_read_u8 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_u8_d16: ImplicitAccess: false Instruction: ds_read_u8_d16 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_read_u8_d16_hi: ImplicitAccess: false Instruction: ds_read_u8_d16_hi IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_rsub_rtn_u32: ImplicitAccess: false Instruction: ds_rsub_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_rsub_rtn_u64: ImplicitAccess: false Instruction: ds_rsub_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_rsub_u32: ImplicitAccess: false Instruction: ds_rsub_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_rsub_u64: ImplicitAccess: false Instruction: ds_rsub_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_sub_rtn_u32: ImplicitAccess: false Instruction: ds_sub_rtn_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_sub_rtn_u64: ImplicitAccess: false Instruction: ds_sub_rtn_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_sub_u32: ImplicitAccess: false Instruction: ds_sub_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_sub_u64: ImplicitAccess: false Instruction: ds_sub_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_swizzle_b32: ImplicitAccess: false Instruction: ds_swizzle_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_wrap_rtn_b32: ImplicitAccess: false Instruction: ds_wrap_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_write2_b32: ImplicitAccess: false Instruction: ds_write2_b32 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_write2_b64: ImplicitAccess: false Instruction: ds_write2_b64 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_write2st64_b32: ImplicitAccess: false Instruction: ds_write2st64_b32 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_write2st64_b64: ImplicitAccess: false Instruction: ds_write2st64_b64 IsBranch: false Latency: -1 MaxLiteral: 255 WaitCount: 1 WaitQueues: - DSQueue ds_write_addtid_b32: ImplicitAccess: false Instruction: ds_write_addtid_b32 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b128: ImplicitAccess: false Instruction: ds_write_b128 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b16: ImplicitAccess: false Instruction: ds_write_b16 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b16_d16_hi: ImplicitAccess: false Instruction: ds_write_b16_d16_hi IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b32: ImplicitAccess: false Instruction: ds_write_b32 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b64: ImplicitAccess: false Instruction: ds_write_b64 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b8: ImplicitAccess: false Instruction: ds_write_b8 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b8_d16_hi: ImplicitAccess: false Instruction: ds_write_b8_d16_hi IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_write_b96: ImplicitAccess: false Instruction: ds_write_b96 IsBranch: false Latency: -1 MaxLiteral: 65535 WaitCount: 1 WaitQueues: - DSQueue ds_wrxchg2_rtn_b32: ImplicitAccess: false Instruction: ds_wrxchg2_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_wrxchg2_rtn_b64: ImplicitAccess: false Instruction: ds_wrxchg2_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_wrxchg2st64_rtn_b32: ImplicitAccess: false Instruction: ds_wrxchg2st64_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_wrxchg2st64_rtn_b64: ImplicitAccess: false Instruction: ds_wrxchg2st64_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_wrxchg_rtn_b32: ImplicitAccess: false Instruction: ds_wrxchg_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_wrxchg_rtn_b64: ImplicitAccess: false Instruction: ds_wrxchg_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_xor_b32: ImplicitAccess: false Instruction: ds_xor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_xor_b64: ImplicitAccess: false Instruction: ds_xor_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_xor_rtn_b32: ImplicitAccess: false Instruction: ds_xor_rtn_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] ds_xor_rtn_b64: ImplicitAccess: false Instruction: ds_xor_rtn_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_add: ImplicitAccess: false Instruction: flat_atomic_add IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_add_f64: ImplicitAccess: false Instruction: flat_atomic_add_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_add_x2: ImplicitAccess: false Instruction: flat_atomic_add_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_and: ImplicitAccess: false Instruction: flat_atomic_and IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_and_x2: ImplicitAccess: false Instruction: flat_atomic_and_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_cmpswap: ImplicitAccess: false Instruction: flat_atomic_cmpswap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_cmpswap_x2: ImplicitAccess: false Instruction: flat_atomic_cmpswap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_dec: ImplicitAccess: false Instruction: flat_atomic_dec IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_dec_x2: ImplicitAccess: false Instruction: flat_atomic_dec_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_inc: ImplicitAccess: false Instruction: flat_atomic_inc IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_inc_x2: ImplicitAccess: false Instruction: flat_atomic_inc_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_max_f64: ImplicitAccess: false Instruction: flat_atomic_max_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_min_f64: ImplicitAccess: false Instruction: flat_atomic_min_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_or: ImplicitAccess: false Instruction: flat_atomic_or IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_or_x2: ImplicitAccess: false Instruction: flat_atomic_or_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_smax: ImplicitAccess: false Instruction: flat_atomic_smax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_smax_x2: ImplicitAccess: false Instruction: flat_atomic_smax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_smin: ImplicitAccess: false Instruction: flat_atomic_smin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_smin_x2: ImplicitAccess: false Instruction: flat_atomic_smin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_sub: ImplicitAccess: false Instruction: flat_atomic_sub IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_sub_x2: ImplicitAccess: false Instruction: flat_atomic_sub_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_swap: ImplicitAccess: false Instruction: flat_atomic_swap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_swap_x2: ImplicitAccess: false Instruction: flat_atomic_swap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_umax: ImplicitAccess: false Instruction: flat_atomic_umax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_umax_x2: ImplicitAccess: false Instruction: flat_atomic_umax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_umin: ImplicitAccess: false Instruction: flat_atomic_umin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_umin_x2: ImplicitAccess: false Instruction: flat_atomic_umin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_xor: ImplicitAccess: false Instruction: flat_atomic_xor IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_atomic_xor_x2: ImplicitAccess: false Instruction: flat_atomic_xor_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_dword: ImplicitAccess: false Instruction: flat_load_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_dwordx2: ImplicitAccess: false Instruction: flat_load_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_dwordx3: ImplicitAccess: false Instruction: flat_load_dwordx3 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_dwordx4: ImplicitAccess: false Instruction: flat_load_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_sbyte: ImplicitAccess: false Instruction: flat_load_sbyte IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_sbyte_d16: ImplicitAccess: false Instruction: flat_load_sbyte_d16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_sbyte_d16_hi: ImplicitAccess: false Instruction: flat_load_sbyte_d16_hi IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_short_d16: ImplicitAccess: false Instruction: flat_load_short_d16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_short_d16_hi: ImplicitAccess: false Instruction: flat_load_short_d16_hi IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_sshort: ImplicitAccess: false Instruction: flat_load_sshort IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_ubyte: ImplicitAccess: false Instruction: flat_load_ubyte IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_ubyte_d16: ImplicitAccess: false Instruction: flat_load_ubyte_d16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_ubyte_d16_hi: ImplicitAccess: false Instruction: flat_load_ubyte_d16_hi IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_load_ushort: ImplicitAccess: false Instruction: flat_load_ushort IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_byte: ImplicitAccess: false Instruction: flat_store_byte IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_byte_d16_hi: ImplicitAccess: false Instruction: flat_store_byte_d16_hi IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_dword: ImplicitAccess: false Instruction: flat_store_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_dwordx2: ImplicitAccess: false Instruction: flat_store_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_dwordx3: ImplicitAccess: false Instruction: flat_store_dwordx3 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_dwordx4: ImplicitAccess: false Instruction: flat_store_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_short: ImplicitAccess: false Instruction: flat_store_short IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] flat_store_short_d16_hi: ImplicitAccess: false Instruction: flat_store_short_d16_hi IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_add: ImplicitAccess: false Instruction: global_atomic_add IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_add_f32: ImplicitAccess: false Instruction: global_atomic_add_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_add_f64: ImplicitAccess: false Instruction: global_atomic_add_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_add_x2: ImplicitAccess: false Instruction: global_atomic_add_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_and: ImplicitAccess: false Instruction: global_atomic_and IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_and_x2: ImplicitAccess: false Instruction: global_atomic_and_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_cmpswap: ImplicitAccess: false Instruction: global_atomic_cmpswap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_cmpswap_x2: ImplicitAccess: false Instruction: global_atomic_cmpswap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_dec: ImplicitAccess: false Instruction: global_atomic_dec IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_dec_x2: ImplicitAccess: false Instruction: global_atomic_dec_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_inc: ImplicitAccess: false Instruction: global_atomic_inc IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_inc_x2: ImplicitAccess: false Instruction: global_atomic_inc_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_max_f64: ImplicitAccess: false Instruction: global_atomic_max_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_min_f64: ImplicitAccess: false Instruction: global_atomic_min_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_or: ImplicitAccess: false Instruction: global_atomic_or IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_or_x2: ImplicitAccess: false Instruction: global_atomic_or_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_pk_add_f16: ImplicitAccess: false Instruction: global_atomic_pk_add_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_smax: ImplicitAccess: false Instruction: global_atomic_smax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_smax_x2: ImplicitAccess: false Instruction: global_atomic_smax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_smin: ImplicitAccess: false Instruction: global_atomic_smin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_smin_x2: ImplicitAccess: false Instruction: global_atomic_smin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_sub: ImplicitAccess: false Instruction: global_atomic_sub IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_sub_x2: ImplicitAccess: false Instruction: global_atomic_sub_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_swap: ImplicitAccess: false Instruction: global_atomic_swap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_swap_x2: ImplicitAccess: false Instruction: global_atomic_swap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_umax: ImplicitAccess: false Instruction: global_atomic_umax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_umax_x2: ImplicitAccess: false Instruction: global_atomic_umax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_umin: ImplicitAccess: false Instruction: global_atomic_umin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_umin_x2: ImplicitAccess: false Instruction: global_atomic_umin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_xor: ImplicitAccess: false Instruction: global_atomic_xor IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_atomic_xor_x2: ImplicitAccess: false Instruction: global_atomic_xor_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] global_load_dword: ImplicitAccess: false Instruction: global_load_dword IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_dwordx2: ImplicitAccess: false Instruction: global_load_dwordx2 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_dwordx3: ImplicitAccess: false Instruction: global_load_dwordx3 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_dwordx4: ImplicitAccess: false Instruction: global_load_dwordx4 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_sbyte: ImplicitAccess: false Instruction: global_load_sbyte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_sbyte_d16: ImplicitAccess: false Instruction: global_load_sbyte_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_sbyte_d16_hi: ImplicitAccess: false Instruction: global_load_sbyte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_short_d16: ImplicitAccess: false Instruction: global_load_short_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_short_d16_hi: ImplicitAccess: false Instruction: global_load_short_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_sshort: ImplicitAccess: false Instruction: global_load_sshort IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_ubyte: ImplicitAccess: false Instruction: global_load_ubyte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_ubyte_d16: ImplicitAccess: false Instruction: global_load_ubyte_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_ubyte_d16_hi: ImplicitAccess: false Instruction: global_load_ubyte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_load_ushort: ImplicitAccess: false Instruction: global_load_ushort IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue global_store_byte: ImplicitAccess: false Instruction: global_store_byte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_byte_d16_hi: ImplicitAccess: false Instruction: global_store_byte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_dword: ImplicitAccess: false Instruction: global_store_dword IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_dwordx2: ImplicitAccess: false Instruction: global_store_dwordx2 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_dwordx3: ImplicitAccess: false Instruction: global_store_dwordx3 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_dwordx4: ImplicitAccess: false Instruction: global_store_dwordx4 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_short: ImplicitAccess: false Instruction: global_store_short IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue global_store_short_d16_hi: ImplicitAccess: false Instruction: global_store_short_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue image_atomic_add: ImplicitAccess: false Instruction: image_atomic_add IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_and: ImplicitAccess: false Instruction: image_atomic_and IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_cmpswap: ImplicitAccess: false Instruction: image_atomic_cmpswap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_dec: ImplicitAccess: false Instruction: image_atomic_dec IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_inc: ImplicitAccess: false Instruction: image_atomic_inc IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_or: ImplicitAccess: false Instruction: image_atomic_or IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_smax: ImplicitAccess: false Instruction: image_atomic_smax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_smin: ImplicitAccess: false Instruction: image_atomic_smin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_sub: ImplicitAccess: false Instruction: image_atomic_sub IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_swap: ImplicitAccess: false Instruction: image_atomic_swap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_umax: ImplicitAccess: false Instruction: image_atomic_umax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_umin: ImplicitAccess: false Instruction: image_atomic_umin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_atomic_xor: ImplicitAccess: false Instruction: image_atomic_xor IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_get_resinfo: ImplicitAccess: false Instruction: image_get_resinfo IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_load: ImplicitAccess: false Instruction: image_load IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_load_mip: ImplicitAccess: false Instruction: image_load_mip IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_load_mip_pck: ImplicitAccess: false Instruction: image_load_mip_pck IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_load_mip_pck_sgn: ImplicitAccess: false Instruction: image_load_mip_pck_sgn IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_load_pck: ImplicitAccess: false Instruction: image_load_pck IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_load_pck_sgn: ImplicitAccess: false Instruction: image_load_pck_sgn IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_sample: ImplicitAccess: false Instruction: image_sample IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_store: ImplicitAccess: false Instruction: image_store IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_store_mip: ImplicitAccess: false Instruction: image_store_mip IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_store_mip_pck: ImplicitAccess: false Instruction: image_store_mip_pck IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] image_store_pck: ImplicitAccess: false Instruction: image_store_pck IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_abs_i32: ImplicitAccess: false Instruction: s_abs_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_absdiff_i32: ImplicitAccess: false Instruction: s_absdiff_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_add_i32: ImplicitAccess: false Instruction: s_add_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_add_u32: ImplicitAccess: false Instruction: s_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_addc_u32: ImplicitAccess: true Instruction: s_addc_u32 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_addk_i32: ImplicitAccess: false Instruction: s_addk_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_and_b32: ImplicitAccess: false Instruction: s_and_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_and_b64: ImplicitAccess: false Instruction: s_and_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_and_saveexec_b64: ImplicitAccess: false Instruction: s_and_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_andn1_saveexec_b64: ImplicitAccess: false Instruction: s_andn1_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_andn1_wrexec_b64: ImplicitAccess: false Instruction: s_andn1_wrexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_andn2_b32: ImplicitAccess: false Instruction: s_andn2_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_andn2_b64: ImplicitAccess: false Instruction: s_andn2_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_andn2_saveexec_b64: ImplicitAccess: false Instruction: s_andn2_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_andn2_wrexec_b64: ImplicitAccess: false Instruction: s_andn2_wrexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ashr_i32: ImplicitAccess: false Instruction: s_ashr_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ashr_i64: ImplicitAccess: false Instruction: s_ashr_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atc_probe: ImplicitAccess: false Instruction: s_atc_probe IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atc_probe_buffer: ImplicitAccess: false Instruction: s_atc_probe_buffer IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_add: ImplicitAccess: false Instruction: s_atomic_add IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_add_x2: ImplicitAccess: false Instruction: s_atomic_add_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_and: ImplicitAccess: false Instruction: s_atomic_and IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_and_x2: ImplicitAccess: false Instruction: s_atomic_and_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_cmpswap: ImplicitAccess: false Instruction: s_atomic_cmpswap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_cmpswap_x2: ImplicitAccess: false Instruction: s_atomic_cmpswap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_dec: ImplicitAccess: false Instruction: s_atomic_dec IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_dec_x2: ImplicitAccess: false Instruction: s_atomic_dec_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_inc: ImplicitAccess: false Instruction: s_atomic_inc IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_inc_x2: ImplicitAccess: false Instruction: s_atomic_inc_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_or: ImplicitAccess: false Instruction: s_atomic_or IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_or_x2: ImplicitAccess: false Instruction: s_atomic_or_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_smax: ImplicitAccess: false Instruction: s_atomic_smax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_smax_x2: ImplicitAccess: false Instruction: s_atomic_smax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_smin: ImplicitAccess: false Instruction: s_atomic_smin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_smin_x2: ImplicitAccess: false Instruction: s_atomic_smin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_sub: ImplicitAccess: false Instruction: s_atomic_sub IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_sub_x2: ImplicitAccess: false Instruction: s_atomic_sub_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_swap: ImplicitAccess: false Instruction: s_atomic_swap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_swap_x2: ImplicitAccess: false Instruction: s_atomic_swap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_umax: ImplicitAccess: false Instruction: s_atomic_umax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_umax_x2: ImplicitAccess: false Instruction: s_atomic_umax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_umin: ImplicitAccess: false Instruction: s_atomic_umin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_umin_x2: ImplicitAccess: false Instruction: s_atomic_umin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_xor: ImplicitAccess: false Instruction: s_atomic_xor IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_atomic_xor_x2: ImplicitAccess: false Instruction: s_atomic_xor_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_barrier: ImplicitAccess: false Instruction: s_barrier IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bcnt0_i32_b32: ImplicitAccess: false Instruction: s_bcnt0_i32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bcnt0_i32_b64: ImplicitAccess: false Instruction: s_bcnt0_i32_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bcnt1_i32_b32: ImplicitAccess: false Instruction: s_bcnt1_i32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bcnt1_i32_b64: ImplicitAccess: false Instruction: s_bcnt1_i32_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bfe_i32: ImplicitAccess: false Instruction: s_bfe_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bfe_i64: ImplicitAccess: false Instruction: s_bfe_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bfe_u32: ImplicitAccess: false Instruction: s_bfe_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bfe_u64: ImplicitAccess: false Instruction: s_bfe_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bfm_b32: ImplicitAccess: false Instruction: s_bfm_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bfm_b64: ImplicitAccess: false Instruction: s_bfm_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitcmp0_b32: ImplicitAccess: false Instruction: s_bitcmp0_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitcmp0_b64: ImplicitAccess: false Instruction: s_bitcmp0_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitcmp1_b32: ImplicitAccess: false Instruction: s_bitcmp1_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitcmp1_b64: ImplicitAccess: false Instruction: s_bitcmp1_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitreplicate_b64_b32: ImplicitAccess: false Instruction: s_bitreplicate_b64_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitset0_b32: ImplicitAccess: false Instruction: s_bitset0_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitset0_b64: ImplicitAccess: false Instruction: s_bitset0_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitset1_b32: ImplicitAccess: false Instruction: s_bitset1_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_bitset1_b64: ImplicitAccess: false Instruction: s_bitset1_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_branch: ImplicitAccess: false Instruction: s_branch IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_brev_b32: ImplicitAccess: false Instruction: s_brev_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_brev_b64: ImplicitAccess: false Instruction: s_brev_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_add: ImplicitAccess: false Instruction: s_buffer_atomic_add IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_add_x2: ImplicitAccess: false Instruction: s_buffer_atomic_add_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_and: ImplicitAccess: false Instruction: s_buffer_atomic_and IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_and_x2: ImplicitAccess: false Instruction: s_buffer_atomic_and_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_cmpswap: ImplicitAccess: false Instruction: s_buffer_atomic_cmpswap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_cmpswap_x2: ImplicitAccess: false Instruction: s_buffer_atomic_cmpswap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_dec: ImplicitAccess: false Instruction: s_buffer_atomic_dec IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_dec_x2: ImplicitAccess: false Instruction: s_buffer_atomic_dec_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_inc: ImplicitAccess: false Instruction: s_buffer_atomic_inc IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_inc_x2: ImplicitAccess: false Instruction: s_buffer_atomic_inc_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_or: ImplicitAccess: false Instruction: s_buffer_atomic_or IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_or_x2: ImplicitAccess: false Instruction: s_buffer_atomic_or_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_smax: ImplicitAccess: false Instruction: s_buffer_atomic_smax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_smax_x2: ImplicitAccess: false Instruction: s_buffer_atomic_smax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_smin: ImplicitAccess: false Instruction: s_buffer_atomic_smin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_smin_x2: ImplicitAccess: false Instruction: s_buffer_atomic_smin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_sub: ImplicitAccess: false Instruction: s_buffer_atomic_sub IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_sub_x2: ImplicitAccess: false Instruction: s_buffer_atomic_sub_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_swap: ImplicitAccess: false Instruction: s_buffer_atomic_swap IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_swap_x2: ImplicitAccess: false Instruction: s_buffer_atomic_swap_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_umax: ImplicitAccess: false Instruction: s_buffer_atomic_umax IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_umax_x2: ImplicitAccess: false Instruction: s_buffer_atomic_umax_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_umin: ImplicitAccess: false Instruction: s_buffer_atomic_umin IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_umin_x2: ImplicitAccess: false Instruction: s_buffer_atomic_umin_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_xor: ImplicitAccess: false Instruction: s_buffer_atomic_xor IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_atomic_xor_x2: ImplicitAccess: false Instruction: s_buffer_atomic_xor_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_buffer_load_dword: ImplicitAccess: false Instruction: s_buffer_load_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_buffer_load_dwordx16: ImplicitAccess: false Instruction: s_buffer_load_dwordx16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_buffer_load_dwordx2: ImplicitAccess: false Instruction: s_buffer_load_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_buffer_load_dwordx4: ImplicitAccess: false Instruction: s_buffer_load_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_buffer_load_dwordx8: ImplicitAccess: false Instruction: s_buffer_load_dwordx8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_buffer_store_dword: ImplicitAccess: false Instruction: s_buffer_store_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_buffer_store_dwordx2: ImplicitAccess: false Instruction: s_buffer_store_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_buffer_store_dwordx4: ImplicitAccess: false Instruction: s_buffer_store_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_call_b64: ImplicitAccess: false Instruction: s_call_b64 IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_cdbgsys: ImplicitAccess: false Instruction: s_cbranch_cdbgsys IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_cdbgsys_and_user: ImplicitAccess: false Instruction: s_cbranch_cdbgsys_and_user IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_cdbgsys_or_user: ImplicitAccess: false Instruction: s_cbranch_cdbgsys_or_user IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_cdbguser: ImplicitAccess: false Instruction: s_cbranch_cdbguser IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_execnz: ImplicitAccess: true Instruction: s_cbranch_execnz IsBranch: true Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_execz: ImplicitAccess: true Instruction: s_cbranch_execz IsBranch: true Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_g_fork: ImplicitAccess: false Instruction: s_cbranch_g_fork IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_i_fork: ImplicitAccess: false Instruction: s_cbranch_i_fork IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_join: ImplicitAccess: false Instruction: s_cbranch_join IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_scc0: ImplicitAccess: true Instruction: s_cbranch_scc0 IsBranch: true Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_scc1: ImplicitAccess: true Instruction: s_cbranch_scc1 IsBranch: true Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_vccnz: ImplicitAccess: true Instruction: s_cbranch_vccnz IsBranch: true Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cbranch_vccz: ImplicitAccess: true Instruction: s_cbranch_vccz IsBranch: true Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmov_b32: ImplicitAccess: true Instruction: s_cmov_b32 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmov_b64: ImplicitAccess: true Instruction: s_cmov_b64 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmovk_i32: ImplicitAccess: true Instruction: s_cmovk_i32 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_eq_i32: ImplicitAccess: false Instruction: s_cmp_eq_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_eq_u32: ImplicitAccess: false Instruction: s_cmp_eq_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_eq_u64: ImplicitAccess: false Instruction: s_cmp_eq_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_ge_i32: ImplicitAccess: false Instruction: s_cmp_ge_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_ge_u32: ImplicitAccess: false Instruction: s_cmp_ge_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_gt_i32: ImplicitAccess: false Instruction: s_cmp_gt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_gt_u32: ImplicitAccess: false Instruction: s_cmp_gt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_le_i32: ImplicitAccess: false Instruction: s_cmp_le_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_le_u32: ImplicitAccess: false Instruction: s_cmp_le_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_lg_i32: ImplicitAccess: false Instruction: s_cmp_lg_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_lg_u32: ImplicitAccess: false Instruction: s_cmp_lg_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_lg_u64: ImplicitAccess: false Instruction: s_cmp_lg_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_lt_i32: ImplicitAccess: false Instruction: s_cmp_lt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmp_lt_u32: ImplicitAccess: false Instruction: s_cmp_lt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_eq_i32: ImplicitAccess: false Instruction: s_cmpk_eq_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_eq_u32: ImplicitAccess: false Instruction: s_cmpk_eq_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_ge_i32: ImplicitAccess: false Instruction: s_cmpk_ge_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_ge_u32: ImplicitAccess: false Instruction: s_cmpk_ge_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_gt_i32: ImplicitAccess: false Instruction: s_cmpk_gt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_gt_u32: ImplicitAccess: false Instruction: s_cmpk_gt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_le_i32: ImplicitAccess: false Instruction: s_cmpk_le_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_le_u32: ImplicitAccess: false Instruction: s_cmpk_le_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_lg_i32: ImplicitAccess: false Instruction: s_cmpk_lg_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_lg_u32: ImplicitAccess: false Instruction: s_cmpk_lg_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_lt_i32: ImplicitAccess: false Instruction: s_cmpk_lt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cmpk_lt_u32: ImplicitAccess: false Instruction: s_cmpk_lt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cselect_b32: ImplicitAccess: true Instruction: s_cselect_b32 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_cselect_b64: ImplicitAccess: true Instruction: s_cselect_b64 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_dcache_discard: ImplicitAccess: false Instruction: s_dcache_discard IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_dcache_discard_x2: ImplicitAccess: false Instruction: s_dcache_discard_x2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_dcache_inv: ImplicitAccess: false Instruction: s_dcache_inv IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_dcache_inv_vol: ImplicitAccess: false Instruction: s_dcache_inv_vol IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_dcache_wb: ImplicitAccess: false Instruction: s_dcache_wb IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_dcache_wb_vol: ImplicitAccess: false Instruction: s_dcache_wb_vol IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_decperflevel: ImplicitAccess: false Instruction: s_decperflevel IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_endpgm: ImplicitAccess: false Instruction: s_endpgm IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: - FinalInstruction s_endpgm_ordered_ps_done: ImplicitAccess: false Instruction: s_endpgm_ordered_ps_done IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_endpgm_saved: ImplicitAccess: false Instruction: s_endpgm_saved IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ff0_i32_b32: ImplicitAccess: false Instruction: s_ff0_i32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ff0_i32_b64: ImplicitAccess: false Instruction: s_ff0_i32_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ff1_i32_b32: ImplicitAccess: false Instruction: s_ff1_i32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ff1_i32_b64: ImplicitAccess: false Instruction: s_ff1_i32_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_flbit_i32: ImplicitAccess: false Instruction: s_flbit_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_flbit_i32_b32: ImplicitAccess: false Instruction: s_flbit_i32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_flbit_i32_b64: ImplicitAccess: false Instruction: s_flbit_i32_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_flbit_i32_i64: ImplicitAccess: false Instruction: s_flbit_i32_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_getpc_b64: ImplicitAccess: false Instruction: s_getpc_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_getreg_b32: ImplicitAccess: false Instruction: s_getreg_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_icache_inv: ImplicitAccess: false Instruction: s_icache_inv IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_incperflevel: ImplicitAccess: false Instruction: s_incperflevel IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_load_dword: ImplicitAccess: false Instruction: s_load_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_load_dwordx16: ImplicitAccess: false Instruction: s_load_dwordx16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_load_dwordx2: ImplicitAccess: false Instruction: s_load_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_load_dwordx4: ImplicitAccess: false Instruction: s_load_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_load_dwordx8: ImplicitAccess: false Instruction: s_load_dwordx8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_lshl1_add_u32: ImplicitAccess: false Instruction: s_lshl1_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshl2_add_u32: ImplicitAccess: false Instruction: s_lshl2_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshl3_add_u32: ImplicitAccess: false Instruction: s_lshl3_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshl4_add_u32: ImplicitAccess: false Instruction: s_lshl4_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshl_b32: ImplicitAccess: false Instruction: s_lshl_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshl_b64: ImplicitAccess: false Instruction: s_lshl_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshr_b32: ImplicitAccess: false Instruction: s_lshr_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_lshr_b64: ImplicitAccess: false Instruction: s_lshr_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_max_i32: ImplicitAccess: false Instruction: s_max_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_max_u32: ImplicitAccess: false Instruction: s_max_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_memrealtime: ImplicitAccess: false Instruction: s_memrealtime IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_memtime: ImplicitAccess: false Instruction: s_memtime IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_min_i32: ImplicitAccess: false Instruction: s_min_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_min_u32: ImplicitAccess: false Instruction: s_min_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_mov_b32: ImplicitAccess: false Instruction: s_mov_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_mov_b64: ImplicitAccess: false Instruction: s_mov_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_movk_i32: ImplicitAccess: false Instruction: s_movk_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_movreld_b32: ImplicitAccess: false Instruction: s_movreld_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_movreld_b64: ImplicitAccess: false Instruction: s_movreld_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_movrels_b32: ImplicitAccess: false Instruction: s_movrels_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_movrels_b64: ImplicitAccess: false Instruction: s_movrels_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_mul_hi_i32: ImplicitAccess: false Instruction: s_mul_hi_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_mul_hi_u32: ImplicitAccess: false Instruction: s_mul_hi_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_mul_i32: ImplicitAccess: false Instruction: s_mul_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_mulk_i32: ImplicitAccess: false Instruction: s_mulk_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nand_b32: ImplicitAccess: false Instruction: s_nand_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nand_b64: ImplicitAccess: false Instruction: s_nand_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nand_saveexec_b64: ImplicitAccess: false Instruction: s_nand_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nop: ImplicitAccess: false Instruction: s_nop IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nor_b32: ImplicitAccess: false Instruction: s_nor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nor_b64: ImplicitAccess: false Instruction: s_nor_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_nor_saveexec_b64: ImplicitAccess: false Instruction: s_nor_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_not_b32: ImplicitAccess: false Instruction: s_not_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_not_b64: ImplicitAccess: false Instruction: s_not_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_or_b32: ImplicitAccess: false Instruction: s_or_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_or_b64: ImplicitAccess: false Instruction: s_or_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_or_saveexec_b64: ImplicitAccess: false Instruction: s_or_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_orn1_saveexec_b64: ImplicitAccess: false Instruction: s_orn1_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_orn2_b32: ImplicitAccess: false Instruction: s_orn2_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_orn2_b64: ImplicitAccess: false Instruction: s_orn2_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_orn2_saveexec_b64: ImplicitAccess: false Instruction: s_orn2_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_pack_hh_b32_b16: ImplicitAccess: false Instruction: s_pack_hh_b32_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_pack_lh_b32_b16: ImplicitAccess: false Instruction: s_pack_lh_b32_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_pack_ll_b32_b16: ImplicitAccess: false Instruction: s_pack_ll_b32_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_quadmask_b32: ImplicitAccess: false Instruction: s_quadmask_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_quadmask_b64: ImplicitAccess: false Instruction: s_quadmask_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_rfe_b64: ImplicitAccess: false Instruction: s_rfe_b64 IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_rfe_restore_b64: ImplicitAccess: false Instruction: s_rfe_restore_b64 IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_scratch_load_dword: ImplicitAccess: false Instruction: s_scratch_load_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_scratch_load_dwordx2: ImplicitAccess: false Instruction: s_scratch_load_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_scratch_load_dwordx4: ImplicitAccess: false Instruction: s_scratch_load_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_scratch_store_dword: ImplicitAccess: false Instruction: s_scratch_store_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SMemQueue s_scratch_store_dwordx2: ImplicitAccess: false Instruction: s_scratch_store_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_scratch_store_dwordx4: ImplicitAccess: false Instruction: s_scratch_store_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 2 WaitQueues: - SMemQueue s_sendmsg: ImplicitAccess: false Instruction: s_sendmsg IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 1 WaitQueues: - SendMsgQueue s_sendmsghalt: ImplicitAccess: false Instruction: s_sendmsghalt IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_set_gpr_idx_idx: ImplicitAccess: false Instruction: s_set_gpr_idx_idx IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_set_gpr_idx_mode: ImplicitAccess: false Instruction: s_set_gpr_idx_mode IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_set_gpr_idx_off: ImplicitAccess: false Instruction: s_set_gpr_idx_off IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_set_gpr_idx_on: ImplicitAccess: false Instruction: s_set_gpr_idx_on IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_sethalt: ImplicitAccess: false Instruction: s_sethalt IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_setkill: ImplicitAccess: false Instruction: s_setkill IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_setpc_b64: ImplicitAccess: false Instruction: s_setpc_b64 IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_setprio: ImplicitAccess: false Instruction: s_setprio IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_setreg_b32: ImplicitAccess: false Instruction: s_setreg_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_setreg_imm32_b32: ImplicitAccess: false Instruction: s_setreg_imm32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_setvskip: ImplicitAccess: false Instruction: s_setvskip IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_sext_i32_i16: ImplicitAccess: false Instruction: s_sext_i32_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_sext_i32_i8: ImplicitAccess: false Instruction: s_sext_i32_i8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_sleep: ImplicitAccess: false Instruction: s_sleep IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_store_dword: ImplicitAccess: false Instruction: s_store_dword IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_store_dwordx2: ImplicitAccess: false Instruction: s_store_dwordx2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_store_dwordx4: ImplicitAccess: false Instruction: s_store_dwordx4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: 0 WaitQueues: - SMemQueue s_sub_i32: ImplicitAccess: false Instruction: s_sub_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_sub_u32: ImplicitAccess: false Instruction: s_sub_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_subb_u32: ImplicitAccess: true Instruction: s_subb_u32 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_swappc_b64: ImplicitAccess: false Instruction: s_swappc_b64 IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_trap: ImplicitAccess: false Instruction: s_trap IsBranch: true Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_ttracedata: ImplicitAccess: false Instruction: s_ttracedata IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_waitcnt: ImplicitAccess: false Instruction: s_waitcnt IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_wakeup: ImplicitAccess: false Instruction: s_wakeup IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_wqm_b32: ImplicitAccess: false Instruction: s_wqm_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_wqm_b64: ImplicitAccess: false Instruction: s_wqm_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_xnor_b32: ImplicitAccess: false Instruction: s_xnor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_xnor_b64: ImplicitAccess: false Instruction: s_xnor_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_xnor_saveexec_b64: ImplicitAccess: false Instruction: s_xnor_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_xor_b32: ImplicitAccess: false Instruction: s_xor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_xor_b64: ImplicitAccess: false Instruction: s_xor_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] s_xor_saveexec_b64: ImplicitAccess: false Instruction: s_xor_saveexec_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] scratch_load_dword: ImplicitAccess: false Instruction: scratch_load_dword IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_dwordx2: ImplicitAccess: false Instruction: scratch_load_dwordx2 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_dwordx3: ImplicitAccess: false Instruction: scratch_load_dwordx3 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_dwordx4: ImplicitAccess: false Instruction: scratch_load_dwordx4 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_sbyte: ImplicitAccess: false Instruction: scratch_load_sbyte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_sbyte_d16: ImplicitAccess: false Instruction: scratch_load_sbyte_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_sbyte_d16_hi: ImplicitAccess: false Instruction: scratch_load_sbyte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_short_d16: ImplicitAccess: false Instruction: scratch_load_short_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_short_d16_hi: ImplicitAccess: false Instruction: scratch_load_short_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_sshort: ImplicitAccess: false Instruction: scratch_load_sshort IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_ubyte: ImplicitAccess: false Instruction: scratch_load_ubyte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_ubyte_d16: ImplicitAccess: false Instruction: scratch_load_ubyte_d16 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_ubyte_d16_hi: ImplicitAccess: false Instruction: scratch_load_ubyte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_load_ushort: ImplicitAccess: false Instruction: scratch_load_ushort IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - LoadQueue scratch_store_byte: ImplicitAccess: false Instruction: scratch_store_byte IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_byte_d16_hi: ImplicitAccess: false Instruction: scratch_store_byte_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_dword: ImplicitAccess: false Instruction: scratch_store_dword IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_dwordx2: ImplicitAccess: false Instruction: scratch_store_dwordx2 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_dwordx3: ImplicitAccess: false Instruction: scratch_store_dwordx3 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_dwordx4: ImplicitAccess: false Instruction: scratch_store_dwordx4 IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_short: ImplicitAccess: false Instruction: scratch_store_short IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue scratch_store_short_d16_hi: ImplicitAccess: false Instruction: scratch_store_short_d16_hi IsBranch: false Latency: -1 MaxLiteral: 4095 WaitCount: 0 WaitQueues: - StoreQueue tbuffer_load_format_d16_x: ImplicitAccess: false Instruction: tbuffer_load_format_d16_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_d16_xy: ImplicitAccess: false Instruction: tbuffer_load_format_d16_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_d16_xyz: ImplicitAccess: false Instruction: tbuffer_load_format_d16_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_d16_xyzw: ImplicitAccess: false Instruction: tbuffer_load_format_d16_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_x: ImplicitAccess: false Instruction: tbuffer_load_format_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_xy: ImplicitAccess: false Instruction: tbuffer_load_format_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_xyz: ImplicitAccess: false Instruction: tbuffer_load_format_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_load_format_xyzw: ImplicitAccess: false Instruction: tbuffer_load_format_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_d16_x: ImplicitAccess: false Instruction: tbuffer_store_format_d16_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_d16_xy: ImplicitAccess: false Instruction: tbuffer_store_format_d16_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_d16_xyz: ImplicitAccess: false Instruction: tbuffer_store_format_d16_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_d16_xyzw: ImplicitAccess: false Instruction: tbuffer_store_format_d16_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_x: ImplicitAccess: false Instruction: tbuffer_store_format_x IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_xy: ImplicitAccess: false Instruction: tbuffer_store_format_xy IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_xyz: ImplicitAccess: false Instruction: tbuffer_store_format_xyz IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] tbuffer_store_format_xyzw: ImplicitAccess: false Instruction: tbuffer_store_format_xyzw IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_accvgpr_mov_b32: ImplicitAccess: false Instruction: v_accvgpr_mov_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_accvgpr_read: ImplicitAccess: false Instruction: v_accvgpr_read IsBranch: false Latency: 1 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_accvgpr_read_b32: ImplicitAccess: false Instruction: v_accvgpr_read_b32 IsBranch: false Latency: 1 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_accvgpr_write: ImplicitAccess: false Instruction: v_accvgpr_write IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_accvgpr_write_b32: ImplicitAccess: false Instruction: v_accvgpr_write_b32 IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_add3_u32: ImplicitAccess: false Instruction: v_add3_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_co_u32: ImplicitAccess: false Instruction: v_add_co_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_f16: ImplicitAccess: false Instruction: v_add_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_f32: ImplicitAccess: false Instruction: v_add_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_f64: ImplicitAccess: false Instruction: v_add_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_i16: ImplicitAccess: false Instruction: v_add_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_i32: ImplicitAccess: false Instruction: v_add_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_lshl_u32: ImplicitAccess: false Instruction: v_add_lshl_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_u16: ImplicitAccess: false Instruction: v_add_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_add_u32: ImplicitAccess: false Instruction: v_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_addc_co_u32: ImplicitAccess: false Instruction: v_addc_co_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_alignbit_b32: ImplicitAccess: false Instruction: v_alignbit_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_alignbyte_b32: ImplicitAccess: false Instruction: v_alignbyte_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_and_b32: ImplicitAccess: false Instruction: v_and_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_and_or_b32: ImplicitAccess: false Instruction: v_and_or_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ashrrev_i16: ImplicitAccess: false Instruction: v_ashrrev_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ashrrev_i32: ImplicitAccess: false Instruction: v_ashrrev_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ashrrev_i64: ImplicitAccess: false Instruction: v_ashrrev_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_bcnt_u32_b32: ImplicitAccess: false Instruction: v_bcnt_u32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_bfe_i32: ImplicitAccess: false Instruction: v_bfe_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_bfe_u32: ImplicitAccess: false Instruction: v_bfe_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_bfi_b32: ImplicitAccess: false Instruction: v_bfi_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_bfm_b32: ImplicitAccess: false Instruction: v_bfm_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_bfrev_b32: ImplicitAccess: false Instruction: v_bfrev_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ceil_f16: ImplicitAccess: false Instruction: v_ceil_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ceil_f32: ImplicitAccess: false Instruction: v_ceil_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ceil_f64: ImplicitAccess: false Instruction: v_ceil_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_clrexcp: ImplicitAccess: false Instruction: v_clrexcp IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_class_f16: ImplicitAccess: false Instruction: v_cmp_class_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_class_f32: ImplicitAccess: false Instruction: v_cmp_class_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_class_f64: ImplicitAccess: false Instruction: v_cmp_class_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_f16: ImplicitAccess: false Instruction: v_cmp_eq_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_f32: ImplicitAccess: false Instruction: v_cmp_eq_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_f64: ImplicitAccess: false Instruction: v_cmp_eq_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_i16: ImplicitAccess: false Instruction: v_cmp_eq_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_i32: ImplicitAccess: false Instruction: v_cmp_eq_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_i64: ImplicitAccess: false Instruction: v_cmp_eq_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_u16: ImplicitAccess: false Instruction: v_cmp_eq_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_u32: ImplicitAccess: false Instruction: v_cmp_eq_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_eq_u64: ImplicitAccess: false Instruction: v_cmp_eq_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_f16: ImplicitAccess: false Instruction: v_cmp_f_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_f32: ImplicitAccess: false Instruction: v_cmp_f_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_f64: ImplicitAccess: false Instruction: v_cmp_f_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_i16: ImplicitAccess: false Instruction: v_cmp_f_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_i32: ImplicitAccess: false Instruction: v_cmp_f_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_i64: ImplicitAccess: false Instruction: v_cmp_f_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_u16: ImplicitAccess: false Instruction: v_cmp_f_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_u32: ImplicitAccess: false Instruction: v_cmp_f_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_f_u64: ImplicitAccess: false Instruction: v_cmp_f_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_f16: ImplicitAccess: false Instruction: v_cmp_ge_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_f32: ImplicitAccess: false Instruction: v_cmp_ge_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_f64: ImplicitAccess: false Instruction: v_cmp_ge_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_i16: ImplicitAccess: false Instruction: v_cmp_ge_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_i32: ImplicitAccess: false Instruction: v_cmp_ge_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_i64: ImplicitAccess: false Instruction: v_cmp_ge_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_u16: ImplicitAccess: false Instruction: v_cmp_ge_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_u32: ImplicitAccess: false Instruction: v_cmp_ge_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ge_u64: ImplicitAccess: false Instruction: v_cmp_ge_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_f16: ImplicitAccess: false Instruction: v_cmp_gt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_f32: ImplicitAccess: false Instruction: v_cmp_gt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_f64: ImplicitAccess: false Instruction: v_cmp_gt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_i16: ImplicitAccess: false Instruction: v_cmp_gt_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_i32: ImplicitAccess: false Instruction: v_cmp_gt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_i64: ImplicitAccess: false Instruction: v_cmp_gt_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_u16: ImplicitAccess: false Instruction: v_cmp_gt_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_u32: ImplicitAccess: false Instruction: v_cmp_gt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_gt_u64: ImplicitAccess: false Instruction: v_cmp_gt_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_f16: ImplicitAccess: false Instruction: v_cmp_le_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_f32: ImplicitAccess: false Instruction: v_cmp_le_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_f64: ImplicitAccess: false Instruction: v_cmp_le_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_i16: ImplicitAccess: false Instruction: v_cmp_le_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_i32: ImplicitAccess: false Instruction: v_cmp_le_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_i64: ImplicitAccess: false Instruction: v_cmp_le_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_u16: ImplicitAccess: false Instruction: v_cmp_le_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_u32: ImplicitAccess: false Instruction: v_cmp_le_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_le_u64: ImplicitAccess: false Instruction: v_cmp_le_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lg_f16: ImplicitAccess: false Instruction: v_cmp_lg_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lg_f32: ImplicitAccess: false Instruction: v_cmp_lg_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lg_f64: ImplicitAccess: false Instruction: v_cmp_lg_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_f16: ImplicitAccess: false Instruction: v_cmp_lt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_f32: ImplicitAccess: false Instruction: v_cmp_lt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_f64: ImplicitAccess: false Instruction: v_cmp_lt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_i16: ImplicitAccess: false Instruction: v_cmp_lt_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_i32: ImplicitAccess: false Instruction: v_cmp_lt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_i64: ImplicitAccess: false Instruction: v_cmp_lt_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_u16: ImplicitAccess: false Instruction: v_cmp_lt_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_u32: ImplicitAccess: false Instruction: v_cmp_lt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_lt_u64: ImplicitAccess: false Instruction: v_cmp_lt_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ne_i16: ImplicitAccess: false Instruction: v_cmp_ne_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ne_i32: ImplicitAccess: false Instruction: v_cmp_ne_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ne_i64: ImplicitAccess: false Instruction: v_cmp_ne_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ne_u16: ImplicitAccess: false Instruction: v_cmp_ne_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ne_u32: ImplicitAccess: false Instruction: v_cmp_ne_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ne_u64: ImplicitAccess: false Instruction: v_cmp_ne_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_neq_f16: ImplicitAccess: false Instruction: v_cmp_neq_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_neq_f32: ImplicitAccess: false Instruction: v_cmp_neq_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_neq_f64: ImplicitAccess: false Instruction: v_cmp_neq_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nge_f16: ImplicitAccess: false Instruction: v_cmp_nge_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nge_f32: ImplicitAccess: false Instruction: v_cmp_nge_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nge_f64: ImplicitAccess: false Instruction: v_cmp_nge_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ngt_f16: ImplicitAccess: false Instruction: v_cmp_ngt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ngt_f32: ImplicitAccess: false Instruction: v_cmp_ngt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_ngt_f64: ImplicitAccess: false Instruction: v_cmp_ngt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nle_f16: ImplicitAccess: false Instruction: v_cmp_nle_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nle_f32: ImplicitAccess: false Instruction: v_cmp_nle_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nle_f64: ImplicitAccess: false Instruction: v_cmp_nle_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nlg_f16: ImplicitAccess: false Instruction: v_cmp_nlg_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nlg_f32: ImplicitAccess: false Instruction: v_cmp_nlg_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nlg_f64: ImplicitAccess: false Instruction: v_cmp_nlg_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nlt_f16: ImplicitAccess: false Instruction: v_cmp_nlt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nlt_f32: ImplicitAccess: false Instruction: v_cmp_nlt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_nlt_f64: ImplicitAccess: false Instruction: v_cmp_nlt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_o_f16: ImplicitAccess: false Instruction: v_cmp_o_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_o_f32: ImplicitAccess: false Instruction: v_cmp_o_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_o_f64: ImplicitAccess: false Instruction: v_cmp_o_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_t_i16: ImplicitAccess: false Instruction: v_cmp_t_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_t_i32: ImplicitAccess: false Instruction: v_cmp_t_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_t_i64: ImplicitAccess: false Instruction: v_cmp_t_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_t_u16: ImplicitAccess: false Instruction: v_cmp_t_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_t_u32: ImplicitAccess: false Instruction: v_cmp_t_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_t_u64: ImplicitAccess: false Instruction: v_cmp_t_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_tru_f16: ImplicitAccess: false Instruction: v_cmp_tru_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_tru_f32: ImplicitAccess: false Instruction: v_cmp_tru_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_tru_f64: ImplicitAccess: false Instruction: v_cmp_tru_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_u_f16: ImplicitAccess: false Instruction: v_cmp_u_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_u_f32: ImplicitAccess: false Instruction: v_cmp_u_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmp_u_f64: ImplicitAccess: false Instruction: v_cmp_u_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_class_f16: ImplicitAccess: false Instruction: v_cmpx_class_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_class_f32: ImplicitAccess: false Instruction: v_cmpx_class_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_class_f64: ImplicitAccess: false Instruction: v_cmpx_class_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_f16: ImplicitAccess: false Instruction: v_cmpx_eq_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_f32: ImplicitAccess: false Instruction: v_cmpx_eq_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_f64: ImplicitAccess: false Instruction: v_cmpx_eq_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_i16: ImplicitAccess: false Instruction: v_cmpx_eq_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_i32: ImplicitAccess: false Instruction: v_cmpx_eq_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_i64: ImplicitAccess: false Instruction: v_cmpx_eq_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_u16: ImplicitAccess: false Instruction: v_cmpx_eq_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_u32: ImplicitAccess: false Instruction: v_cmpx_eq_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_eq_u64: ImplicitAccess: false Instruction: v_cmpx_eq_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_f16: ImplicitAccess: false Instruction: v_cmpx_f_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_f32: ImplicitAccess: false Instruction: v_cmpx_f_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_f64: ImplicitAccess: false Instruction: v_cmpx_f_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_i16: ImplicitAccess: false Instruction: v_cmpx_f_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_i32: ImplicitAccess: false Instruction: v_cmpx_f_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_i64: ImplicitAccess: false Instruction: v_cmpx_f_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_u16: ImplicitAccess: false Instruction: v_cmpx_f_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_u32: ImplicitAccess: false Instruction: v_cmpx_f_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_f_u64: ImplicitAccess: false Instruction: v_cmpx_f_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_f16: ImplicitAccess: false Instruction: v_cmpx_ge_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_f32: ImplicitAccess: false Instruction: v_cmpx_ge_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_f64: ImplicitAccess: false Instruction: v_cmpx_ge_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_i16: ImplicitAccess: false Instruction: v_cmpx_ge_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_i32: ImplicitAccess: false Instruction: v_cmpx_ge_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_i64: ImplicitAccess: false Instruction: v_cmpx_ge_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_u16: ImplicitAccess: false Instruction: v_cmpx_ge_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_u32: ImplicitAccess: false Instruction: v_cmpx_ge_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ge_u64: ImplicitAccess: false Instruction: v_cmpx_ge_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_f16: ImplicitAccess: false Instruction: v_cmpx_gt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_f32: ImplicitAccess: false Instruction: v_cmpx_gt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_f64: ImplicitAccess: false Instruction: v_cmpx_gt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_i16: ImplicitAccess: false Instruction: v_cmpx_gt_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_i32: ImplicitAccess: false Instruction: v_cmpx_gt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_i64: ImplicitAccess: false Instruction: v_cmpx_gt_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_u16: ImplicitAccess: false Instruction: v_cmpx_gt_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_u32: ImplicitAccess: false Instruction: v_cmpx_gt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_gt_u64: ImplicitAccess: false Instruction: v_cmpx_gt_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_f16: ImplicitAccess: false Instruction: v_cmpx_le_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_f32: ImplicitAccess: false Instruction: v_cmpx_le_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_f64: ImplicitAccess: false Instruction: v_cmpx_le_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_i16: ImplicitAccess: false Instruction: v_cmpx_le_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_i32: ImplicitAccess: false Instruction: v_cmpx_le_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_i64: ImplicitAccess: false Instruction: v_cmpx_le_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_u16: ImplicitAccess: false Instruction: v_cmpx_le_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_u32: ImplicitAccess: false Instruction: v_cmpx_le_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_le_u64: ImplicitAccess: false Instruction: v_cmpx_le_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lg_f16: ImplicitAccess: false Instruction: v_cmpx_lg_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lg_f32: ImplicitAccess: false Instruction: v_cmpx_lg_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lg_f64: ImplicitAccess: false Instruction: v_cmpx_lg_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_f16: ImplicitAccess: false Instruction: v_cmpx_lt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_f32: ImplicitAccess: false Instruction: v_cmpx_lt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_f64: ImplicitAccess: false Instruction: v_cmpx_lt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_i16: ImplicitAccess: false Instruction: v_cmpx_lt_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_i32: ImplicitAccess: false Instruction: v_cmpx_lt_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_i64: ImplicitAccess: false Instruction: v_cmpx_lt_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_u16: ImplicitAccess: false Instruction: v_cmpx_lt_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_u32: ImplicitAccess: false Instruction: v_cmpx_lt_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_lt_u64: ImplicitAccess: false Instruction: v_cmpx_lt_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ne_i16: ImplicitAccess: false Instruction: v_cmpx_ne_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ne_i32: ImplicitAccess: false Instruction: v_cmpx_ne_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ne_i64: ImplicitAccess: false Instruction: v_cmpx_ne_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ne_u16: ImplicitAccess: false Instruction: v_cmpx_ne_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ne_u32: ImplicitAccess: false Instruction: v_cmpx_ne_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ne_u64: ImplicitAccess: false Instruction: v_cmpx_ne_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_neq_f16: ImplicitAccess: false Instruction: v_cmpx_neq_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_neq_f32: ImplicitAccess: false Instruction: v_cmpx_neq_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_neq_f64: ImplicitAccess: false Instruction: v_cmpx_neq_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nge_f16: ImplicitAccess: false Instruction: v_cmpx_nge_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nge_f32: ImplicitAccess: false Instruction: v_cmpx_nge_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nge_f64: ImplicitAccess: false Instruction: v_cmpx_nge_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ngt_f16: ImplicitAccess: false Instruction: v_cmpx_ngt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ngt_f32: ImplicitAccess: false Instruction: v_cmpx_ngt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_ngt_f64: ImplicitAccess: false Instruction: v_cmpx_ngt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nle_f16: ImplicitAccess: false Instruction: v_cmpx_nle_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nle_f32: ImplicitAccess: false Instruction: v_cmpx_nle_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nle_f64: ImplicitAccess: false Instruction: v_cmpx_nle_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nlg_f16: ImplicitAccess: false Instruction: v_cmpx_nlg_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nlg_f32: ImplicitAccess: false Instruction: v_cmpx_nlg_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nlg_f64: ImplicitAccess: false Instruction: v_cmpx_nlg_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nlt_f16: ImplicitAccess: false Instruction: v_cmpx_nlt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nlt_f32: ImplicitAccess: false Instruction: v_cmpx_nlt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_nlt_f64: ImplicitAccess: false Instruction: v_cmpx_nlt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_o_f16: ImplicitAccess: false Instruction: v_cmpx_o_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_o_f32: ImplicitAccess: false Instruction: v_cmpx_o_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_o_f64: ImplicitAccess: false Instruction: v_cmpx_o_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_t_i16: ImplicitAccess: false Instruction: v_cmpx_t_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_t_i32: ImplicitAccess: false Instruction: v_cmpx_t_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_t_i64: ImplicitAccess: false Instruction: v_cmpx_t_i64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_t_u16: ImplicitAccess: false Instruction: v_cmpx_t_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_t_u32: ImplicitAccess: false Instruction: v_cmpx_t_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_t_u64: ImplicitAccess: false Instruction: v_cmpx_t_u64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_tru_f16: ImplicitAccess: false Instruction: v_cmpx_tru_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_tru_f32: ImplicitAccess: false Instruction: v_cmpx_tru_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_tru_f64: ImplicitAccess: false Instruction: v_cmpx_tru_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_u_f16: ImplicitAccess: false Instruction: v_cmpx_u_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_u_f32: ImplicitAccess: false Instruction: v_cmpx_u_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cmpx_u_f64: ImplicitAccess: false Instruction: v_cmpx_u_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cndmask_b32: ImplicitAccess: false Instruction: v_cndmask_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cos_f16: ImplicitAccess: false Instruction: v_cos_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cos_f32: ImplicitAccess: false Instruction: v_cos_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cubeid_f32: ImplicitAccess: false Instruction: v_cubeid_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cubema_f32: ImplicitAccess: false Instruction: v_cubema_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cubesc_f32: ImplicitAccess: false Instruction: v_cubesc_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cubetc_f32: ImplicitAccess: false Instruction: v_cubetc_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f16_f32: ImplicitAccess: false Instruction: v_cvt_f16_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f16_i16: ImplicitAccess: false Instruction: v_cvt_f16_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f16_u16: ImplicitAccess: false Instruction: v_cvt_f16_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_f16: ImplicitAccess: false Instruction: v_cvt_f32_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_f64: ImplicitAccess: false Instruction: v_cvt_f32_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_i32: ImplicitAccess: false Instruction: v_cvt_f32_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_u32: ImplicitAccess: false Instruction: v_cvt_f32_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_ubyte0: ImplicitAccess: false Instruction: v_cvt_f32_ubyte0 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_ubyte1: ImplicitAccess: false Instruction: v_cvt_f32_ubyte1 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_ubyte2: ImplicitAccess: false Instruction: v_cvt_f32_ubyte2 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f32_ubyte3: ImplicitAccess: false Instruction: v_cvt_f32_ubyte3 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f64_f32: ImplicitAccess: false Instruction: v_cvt_f64_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f64_i32: ImplicitAccess: false Instruction: v_cvt_f64_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_f64_u32: ImplicitAccess: false Instruction: v_cvt_f64_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_flr_i32_f32: ImplicitAccess: false Instruction: v_cvt_flr_i32_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_i16_f16: ImplicitAccess: false Instruction: v_cvt_i16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_i32_f32: ImplicitAccess: false Instruction: v_cvt_i32_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_i32_f64: ImplicitAccess: false Instruction: v_cvt_i32_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_norm_i16_f16: ImplicitAccess: false Instruction: v_cvt_norm_i16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_norm_u16_f16: ImplicitAccess: false Instruction: v_cvt_norm_u16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_off_f32_i4: ImplicitAccess: false Instruction: v_cvt_off_f32_i4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pk_i16_i32: ImplicitAccess: false Instruction: v_cvt_pk_i16_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pk_u16_u32: ImplicitAccess: false Instruction: v_cvt_pk_u16_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pk_u8_f32: ImplicitAccess: false Instruction: v_cvt_pk_u8_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pkaccum_u8_f32: ImplicitAccess: false Instruction: v_cvt_pkaccum_u8_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pknorm_i16_f16: ImplicitAccess: false Instruction: v_cvt_pknorm_i16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pknorm_i16_f32: ImplicitAccess: false Instruction: v_cvt_pknorm_i16_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pknorm_u16_f16: ImplicitAccess: false Instruction: v_cvt_pknorm_u16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pknorm_u16_f32: ImplicitAccess: false Instruction: v_cvt_pknorm_u16_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_pkrtz_f16_f32: ImplicitAccess: false Instruction: v_cvt_pkrtz_f16_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_rpi_i32_f32: ImplicitAccess: false Instruction: v_cvt_rpi_i32_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_u16_f16: ImplicitAccess: false Instruction: v_cvt_u16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_u32_f32: ImplicitAccess: false Instruction: v_cvt_u32_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_cvt_u32_f64: ImplicitAccess: false Instruction: v_cvt_u32_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_fixup_f16: ImplicitAccess: false Instruction: v_div_fixup_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_fixup_f32: ImplicitAccess: false Instruction: v_div_fixup_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_fixup_f64: ImplicitAccess: false Instruction: v_div_fixup_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_fixup_legacy_f16: ImplicitAccess: false Instruction: v_div_fixup_legacy_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_fmas_f32: ImplicitAccess: false Instruction: v_div_fmas_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_fmas_f64: ImplicitAccess: false Instruction: v_div_fmas_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_scale_f32: ImplicitAccess: false Instruction: v_div_scale_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_div_scale_f64: ImplicitAccess: false Instruction: v_div_scale_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot2_f32_f16: ImplicitAccess: false Instruction: v_dot2_f32_f16 IsBranch: false Latency: 1 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_dot2_i32_i16: ImplicitAccess: false Instruction: v_dot2_i32_i16 IsBranch: false Latency: 1 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_dot2_u32_u16: ImplicitAccess: false Instruction: v_dot2_u32_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot2c_f32_f16: ImplicitAccess: false Instruction: v_dot2c_f32_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot2c_i32_i16: ImplicitAccess: false Instruction: v_dot2c_i32_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot4_i32_i8: ImplicitAccess: false Instruction: v_dot4_i32_i8 IsBranch: false Latency: 1 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_dot4_u32_u8: ImplicitAccess: false Instruction: v_dot4_u32_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot4c_i32_i8: ImplicitAccess: false Instruction: v_dot4c_i32_i8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot8_i32_i4: ImplicitAccess: false Instruction: v_dot8_i32_i4 IsBranch: false Latency: 1 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_dot8_u32_u4: ImplicitAccess: false Instruction: v_dot8_u32_u4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_dot8c_i32_i4: ImplicitAccess: false Instruction: v_dot8c_i32_i4 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_exp_f16: ImplicitAccess: false Instruction: v_exp_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_exp_f32: ImplicitAccess: false Instruction: v_exp_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ffbh_i32: ImplicitAccess: false Instruction: v_ffbh_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ffbh_u32: ImplicitAccess: false Instruction: v_ffbh_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ffbl_b32: ImplicitAccess: false Instruction: v_ffbl_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_floor_f16: ImplicitAccess: false Instruction: v_floor_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_floor_f32: ImplicitAccess: false Instruction: v_floor_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_floor_f64: ImplicitAccess: false Instruction: v_floor_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fma_f16: ImplicitAccess: false Instruction: v_fma_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fma_f32: ImplicitAccess: false Instruction: v_fma_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fma_f64: ImplicitAccess: false Instruction: v_fma_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fma_legacy_f16: ImplicitAccess: false Instruction: v_fma_legacy_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fma_mix_f32: ImplicitAccess: false Instruction: v_fma_mix_f32 IsBranch: false Latency: -1 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fmac_f32: ImplicitAccess: false Instruction: v_fmac_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fmac_f64: ImplicitAccess: false Instruction: v_fmac_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fract_f16: ImplicitAccess: false Instruction: v_fract_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fract_f32: ImplicitAccess: false Instruction: v_fract_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_fract_f64: ImplicitAccess: false Instruction: v_fract_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_frexp_exp_i16_f16: ImplicitAccess: false Instruction: v_frexp_exp_i16_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_frexp_exp_i32_f32: ImplicitAccess: false Instruction: v_frexp_exp_i32_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_frexp_exp_i32_f64: ImplicitAccess: false Instruction: v_frexp_exp_i32_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_frexp_mant_f16: ImplicitAccess: false Instruction: v_frexp_mant_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_frexp_mant_f32: ImplicitAccess: false Instruction: v_frexp_mant_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_frexp_mant_f64: ImplicitAccess: false Instruction: v_frexp_mant_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ldexp_f16: ImplicitAccess: false Instruction: v_ldexp_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ldexp_f32: ImplicitAccess: false Instruction: v_ldexp_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_ldexp_f64: ImplicitAccess: false Instruction: v_ldexp_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lerp_u8: ImplicitAccess: false Instruction: v_lerp_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_log_f16: ImplicitAccess: false Instruction: v_log_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_log_f32: ImplicitAccess: false Instruction: v_log_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshl_add_u32: ImplicitAccess: false Instruction: v_lshl_add_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshl_or_b32: ImplicitAccess: false Instruction: v_lshl_or_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshlrev_b16: ImplicitAccess: false Instruction: v_lshlrev_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshlrev_b32: ImplicitAccess: false Instruction: v_lshlrev_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshlrev_b64: ImplicitAccess: false Instruction: v_lshlrev_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshrrev_b16: ImplicitAccess: false Instruction: v_lshrrev_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshrrev_b32: ImplicitAccess: false Instruction: v_lshrrev_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_lshrrev_b64: ImplicitAccess: false Instruction: v_lshrrev_b64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mac_f16: ImplicitAccess: false Instruction: v_mac_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mac_f32: ImplicitAccess: false Instruction: v_mac_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_f16: ImplicitAccess: false Instruction: v_mad_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_f32: ImplicitAccess: false Instruction: v_mad_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_i16: ImplicitAccess: false Instruction: v_mad_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_i32_i16: ImplicitAccess: false Instruction: v_mad_i32_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_i32_i24: ImplicitAccess: false Instruction: v_mad_i32_i24 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_i64_i32: ImplicitAccess: false Instruction: v_mad_i64_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_legacy_f16: ImplicitAccess: false Instruction: v_mad_legacy_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_legacy_f32: ImplicitAccess: false Instruction: v_mad_legacy_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_legacy_i16: ImplicitAccess: false Instruction: v_mad_legacy_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_legacy_u16: ImplicitAccess: false Instruction: v_mad_legacy_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_mix_f32: ImplicitAccess: false Instruction: v_mad_mix_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_mixhi_f16: ImplicitAccess: false Instruction: v_mad_mixhi_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_mixlo_f16: ImplicitAccess: false Instruction: v_mad_mixlo_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_u16: ImplicitAccess: false Instruction: v_mad_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_u32_u16: ImplicitAccess: false Instruction: v_mad_u32_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_u32_u24: ImplicitAccess: false Instruction: v_mad_u32_u24 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mad_u64_u32: ImplicitAccess: false Instruction: v_mad_u64_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_madak_f16: ImplicitAccess: false Instruction: v_madak_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_madak_f32: ImplicitAccess: false Instruction: v_madak_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_madmk_f16: ImplicitAccess: false Instruction: v_madmk_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_madmk_f32: ImplicitAccess: false Instruction: v_madmk_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max3_f16: ImplicitAccess: false Instruction: v_max3_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max3_f32: ImplicitAccess: false Instruction: v_max3_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max3_i16: ImplicitAccess: false Instruction: v_max3_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max3_i32: ImplicitAccess: false Instruction: v_max3_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max3_u16: ImplicitAccess: false Instruction: v_max3_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max3_u32: ImplicitAccess: false Instruction: v_max3_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_f16: ImplicitAccess: false Instruction: v_max_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_f32: ImplicitAccess: false Instruction: v_max_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_f64: ImplicitAccess: false Instruction: v_max_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_i16: ImplicitAccess: false Instruction: v_max_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_i32: ImplicitAccess: false Instruction: v_max_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_u16: ImplicitAccess: false Instruction: v_max_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_max_u32: ImplicitAccess: false Instruction: v_max_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mbcnt_hi_u32_b32: ImplicitAccess: false Instruction: v_mbcnt_hi_u32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mbcnt_lo_u32_b32: ImplicitAccess: false Instruction: v_mbcnt_lo_u32_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_med3_f16: ImplicitAccess: false Instruction: v_med3_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_med3_f32: ImplicitAccess: false Instruction: v_med3_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_med3_i16: ImplicitAccess: false Instruction: v_med3_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_med3_i32: ImplicitAccess: false Instruction: v_med3_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_med3_u16: ImplicitAccess: false Instruction: v_med3_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_med3_u32: ImplicitAccess: false Instruction: v_med3_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mfma_f32_16x16x16bf16_1k: ImplicitAccess: false Instruction: v_mfma_f32_16x16x16bf16_1k IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_16x16x16f16: ImplicitAccess: false Instruction: v_mfma_f32_16x16x16f16 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_16x16x1f32: ImplicitAccess: false Instruction: v_mfma_f32_16x16x1f32 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_16x16x2bf16: ImplicitAccess: false Instruction: v_mfma_f32_16x16x2bf16 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_16x16x4bf16_1k: ImplicitAccess: false Instruction: v_mfma_f32_16x16x4bf16_1k IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mfma_f32_16x16x4f16: ImplicitAccess: false Instruction: v_mfma_f32_16x16x4f16 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_16x16x4f32: ImplicitAccess: false Instruction: v_mfma_f32_16x16x4f32 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_16x16x8bf16: ImplicitAccess: false Instruction: v_mfma_f32_16x16x8bf16 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x1f32: ImplicitAccess: false Instruction: v_mfma_f32_32x32x1f32 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x2bf16: ImplicitAccess: false Instruction: v_mfma_f32_32x32x2bf16 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x2f32: ImplicitAccess: false Instruction: v_mfma_f32_32x32x2f32 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x4bf16: ImplicitAccess: false Instruction: v_mfma_f32_32x32x4bf16 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x4bf16_1k: ImplicitAccess: false Instruction: v_mfma_f32_32x32x4bf16_1k IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x4f16: ImplicitAccess: false Instruction: v_mfma_f32_32x32x4f16 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x8bf16_1k: ImplicitAccess: false Instruction: v_mfma_f32_32x32x8bf16_1k IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_32x32x8f16: ImplicitAccess: false Instruction: v_mfma_f32_32x32x8f16 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_4x4x1f32: ImplicitAccess: false Instruction: v_mfma_f32_4x4x1f32 IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_4x4x2bf16: ImplicitAccess: false Instruction: v_mfma_f32_4x4x2bf16 IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_4x4x4bf16_1k: ImplicitAccess: false Instruction: v_mfma_f32_4x4x4bf16_1k IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f32_4x4x4f16: ImplicitAccess: false Instruction: v_mfma_f32_4x4x4f16 IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f64_16x16x4f64: ImplicitAccess: false Instruction: v_mfma_f64_16x16x4f64 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_f64_4x4x4f64: ImplicitAccess: false Instruction: v_mfma_f64_4x4x4f64 IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_i32_16x16x16i8: ImplicitAccess: false Instruction: v_mfma_i32_16x16x16i8 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_i32_16x16x4i8: ImplicitAccess: false Instruction: v_mfma_i32_16x16x4i8 IsBranch: false Latency: 8 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_i32_32x32x4i8: ImplicitAccess: false Instruction: v_mfma_i32_32x32x4i8 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_i32_32x32x8i8: ImplicitAccess: false Instruction: v_mfma_i32_32x32x8i8 IsBranch: false Latency: 16 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_mfma_i32_4x4x4i8: ImplicitAccess: false Instruction: v_mfma_i32_4x4x4i8 IsBranch: false Latency: 2 MaxLiteral: 0 WaitCount: 0 WaitQueues: [] v_min3_f16: ImplicitAccess: false Instruction: v_min3_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min3_f32: ImplicitAccess: false Instruction: v_min3_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min3_i16: ImplicitAccess: false Instruction: v_min3_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min3_i32: ImplicitAccess: false Instruction: v_min3_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min3_u16: ImplicitAccess: false Instruction: v_min3_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min3_u32: ImplicitAccess: false Instruction: v_min3_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_f16: ImplicitAccess: false Instruction: v_min_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_f32: ImplicitAccess: false Instruction: v_min_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_f64: ImplicitAccess: false Instruction: v_min_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_i16: ImplicitAccess: false Instruction: v_min_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_i32: ImplicitAccess: false Instruction: v_min_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_u16: ImplicitAccess: false Instruction: v_min_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_min_u32: ImplicitAccess: false Instruction: v_min_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mov_b32: ImplicitAccess: false Instruction: v_mov_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mqsad_pk_u16_u8: ImplicitAccess: false Instruction: v_mqsad_pk_u16_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mqsad_u32_u8: ImplicitAccess: false Instruction: v_mqsad_u32_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_msad_u8: ImplicitAccess: false Instruction: v_msad_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_f16: ImplicitAccess: false Instruction: v_mul_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_f32: ImplicitAccess: false Instruction: v_mul_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_f64: ImplicitAccess: false Instruction: v_mul_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_hi_i32: ImplicitAccess: false Instruction: v_mul_hi_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_hi_i32_i24: ImplicitAccess: false Instruction: v_mul_hi_i32_i24 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_hi_u32: ImplicitAccess: false Instruction: v_mul_hi_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_hi_u32_u24: ImplicitAccess: false Instruction: v_mul_hi_u32_u24 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_i32_i24: ImplicitAccess: false Instruction: v_mul_i32_i24 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_legacy_f32: ImplicitAccess: false Instruction: v_mul_legacy_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_lo_u16: ImplicitAccess: false Instruction: v_mul_lo_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_lo_u32: ImplicitAccess: false Instruction: v_mul_lo_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_mul_u32_u24: ImplicitAccess: false Instruction: v_mul_u32_u24 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_nop: ImplicitAccess: false Instruction: v_nop IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_not_b32: ImplicitAccess: false Instruction: v_not_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_or3_b32: ImplicitAccess: false Instruction: v_or3_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_or_b32: ImplicitAccess: false Instruction: v_or_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pack_b32_f16: ImplicitAccess: false Instruction: v_pack_b32_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_perm_b32: ImplicitAccess: false Instruction: v_perm_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_add_f16: ImplicitAccess: false Instruction: v_pk_add_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_add_f32: ImplicitAccess: false Instruction: v_pk_add_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_add_i16: ImplicitAccess: false Instruction: v_pk_add_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_add_u16: ImplicitAccess: false Instruction: v_pk_add_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_ashrrev_i16: ImplicitAccess: false Instruction: v_pk_ashrrev_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_fma_f16: ImplicitAccess: false Instruction: v_pk_fma_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_fma_f32: ImplicitAccess: false Instruction: v_pk_fma_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_fmac_f16: ImplicitAccess: false Instruction: v_pk_fmac_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_lshlrev_b16: ImplicitAccess: false Instruction: v_pk_lshlrev_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_lshrrev_b16: ImplicitAccess: false Instruction: v_pk_lshrrev_b16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_mad_i16: ImplicitAccess: false Instruction: v_pk_mad_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_mad_u16: ImplicitAccess: false Instruction: v_pk_mad_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_max_f16: ImplicitAccess: false Instruction: v_pk_max_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_max_i16: ImplicitAccess: false Instruction: v_pk_max_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_max_u16: ImplicitAccess: false Instruction: v_pk_max_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_min_f16: ImplicitAccess: false Instruction: v_pk_min_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_min_i16: ImplicitAccess: false Instruction: v_pk_min_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_min_u16: ImplicitAccess: false Instruction: v_pk_min_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_mov_b32: ImplicitAccess: false Instruction: v_pk_mov_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_mul_f16: ImplicitAccess: false Instruction: v_pk_mul_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_mul_f32: ImplicitAccess: false Instruction: v_pk_mul_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_mul_lo_u16: ImplicitAccess: false Instruction: v_pk_mul_lo_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_sub_i16: ImplicitAccess: false Instruction: v_pk_sub_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_pk_sub_u16: ImplicitAccess: false Instruction: v_pk_sub_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_qsad_pk_u16_u8: ImplicitAccess: false Instruction: v_qsad_pk_u16_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rcp_f16: ImplicitAccess: false Instruction: v_rcp_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rcp_f32: ImplicitAccess: false Instruction: v_rcp_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rcp_f64: ImplicitAccess: false Instruction: v_rcp_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rcp_iflag_f32: ImplicitAccess: false Instruction: v_rcp_iflag_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_readfirstlane_b32: ImplicitAccess: false Instruction: v_readfirstlane_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_readlane_b32: ImplicitAccess: false Instruction: v_readlane_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rndne_f16: ImplicitAccess: false Instruction: v_rndne_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rndne_f32: ImplicitAccess: false Instruction: v_rndne_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rndne_f64: ImplicitAccess: false Instruction: v_rndne_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rsq_f16: ImplicitAccess: false Instruction: v_rsq_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rsq_f32: ImplicitAccess: false Instruction: v_rsq_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_rsq_f64: ImplicitAccess: false Instruction: v_rsq_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sad_hi_u8: ImplicitAccess: false Instruction: v_sad_hi_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sad_u16: ImplicitAccess: false Instruction: v_sad_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sad_u32: ImplicitAccess: false Instruction: v_sad_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sad_u8: ImplicitAccess: false Instruction: v_sad_u8 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sat_pk_u8_i16: ImplicitAccess: false Instruction: v_sat_pk_u8_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_screen_partition_4se_b32: ImplicitAccess: false Instruction: v_screen_partition_4se_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sin_f16: ImplicitAccess: false Instruction: v_sin_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sin_f32: ImplicitAccess: false Instruction: v_sin_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sqrt_f16: ImplicitAccess: false Instruction: v_sqrt_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sqrt_f32: ImplicitAccess: false Instruction: v_sqrt_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sqrt_f64: ImplicitAccess: false Instruction: v_sqrt_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_co_u32: ImplicitAccess: false Instruction: v_sub_co_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_f16: ImplicitAccess: false Instruction: v_sub_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_f32: ImplicitAccess: false Instruction: v_sub_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_i16: ImplicitAccess: false Instruction: v_sub_i16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_i32: ImplicitAccess: false Instruction: v_sub_i32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_u16: ImplicitAccess: false Instruction: v_sub_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_sub_u32: ImplicitAccess: false Instruction: v_sub_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subb_co_u32: ImplicitAccess: false Instruction: v_subb_co_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subbrev_co_u32: ImplicitAccess: false Instruction: v_subbrev_co_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subrev_co_u32: ImplicitAccess: false Instruction: v_subrev_co_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subrev_f16: ImplicitAccess: false Instruction: v_subrev_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subrev_f32: ImplicitAccess: false Instruction: v_subrev_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subrev_u16: ImplicitAccess: false Instruction: v_subrev_u16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_subrev_u32: ImplicitAccess: false Instruction: v_subrev_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_swap_b32: ImplicitAccess: false Instruction: v_swap_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_trig_preop_f64: ImplicitAccess: false Instruction: v_trig_preop_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_trunc_f16: ImplicitAccess: false Instruction: v_trunc_f16 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_trunc_f32: ImplicitAccess: false Instruction: v_trunc_f32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_trunc_f64: ImplicitAccess: false Instruction: v_trunc_f64 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_writelane_b32: ImplicitAccess: false Instruction: v_writelane_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_xad_u32: ImplicitAccess: false Instruction: v_xad_u32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_xnor_b32: ImplicitAccess: false Instruction: v_xnor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: [] v_xor_b32: ImplicitAccess: false Instruction: v_xor_b32 IsBranch: false Latency: 0 MaxLiteral: 0 WaitCount: -1 WaitQueues: []