// REQUIRES: riscv-registered-target // RUN: %clang --target=riscv64 -mcpu=xt-c910v2 --print-enabled-extensions | FileCheck %s // CHECK: Extensions enabled for the given RISC-V target // CHECK-EMPTY: // CHECK-NEXT: Name Version Description // CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) // CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) // CHECK-NEXT: a 2.1 'A' (Atomic Instructions) // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) // CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) // CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) // CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) // CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) // CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) // CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) // CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores) // CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) // CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) // CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) // CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) // CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) // CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) // CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes) // CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) // CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) // CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) // CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) // CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) // CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) // CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) // CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) // CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) // CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) // CHECK-NEXT: zbkc 1.0 'Zbkc' (Carry-less multiply instructions for Cryptography) // CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) // CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads) // CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering) // CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero) // CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts) // CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values) // CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode) // CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported) // CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits) // CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported) // CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) // CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) // CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) // CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) // CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) // CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) // CHECK-NEXT: xtheadcmo 1.0 'XTHeadCmo' (T-Head cache management instructions) // CHECK-NEXT: xtheadcondmov 1.0 'XTHeadCondMov' (T-Head conditional move instructions) // CHECK-NEXT: xtheadfmemidx 1.0 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations) // CHECK-NEXT: xtheadmac 1.0 'XTHeadMac' (T-Head Multiply-Accumulate Instructions) // CHECK-NEXT: xtheadmemidx 1.0 'XTHeadMemIdx' (T-Head Indexed Memory Operations) // CHECK-NEXT: xtheadmempair 1.0 'XTHeadMemPair' (T-Head two-GPR Memory Operations) // CHECK-NEXT: xtheadsync 1.0 'XTHeadSync' (T-Head multicore synchronization instructions) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: // CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkc1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_xtheadba1p0_xtheadbb1p0_xtheadbs1p0_xtheadcmo1p0_xtheadcondmov1p0_xtheadfmemidx1p0_xtheadmac1p0_xtheadmemidx1p0_xtheadmempair1p0_xtheadsync1p0