; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV32ZBB
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV64ZBB

define i32 @rotl_i32_3rd_arg_const(i32 %a) {
; RV32-LABEL: 'rotl_i32_3rd_arg_const'
; RV32-NEXT:  Cost Model: Found costs of 3 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64-LABEL: 'rotl_i32_3rd_arg_const'
; RV64-NEXT:  Cost Model: Found costs of 3 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_const'
; RV32ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_const'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
  %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
  ret i32 %r
}

define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
; RV32-LABEL: 'rotl_i32_3rd_arg_var'
; RV32-NEXT:  Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64-LABEL: 'rotl_i32_3rd_arg_var'
; RV64-NEXT:  Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_var'
; RV32ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_var'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
  %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
  ret i32 %r
}

define i64 @rotl_i64_3rd_arg_const(i64 %a) {
; RV32-LABEL: 'rotl_i64_3rd_arg_const'
; RV32-NEXT:  Cost Model: Found costs of RThru:6 CodeSize:3 Lat:3 SizeLat:3 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64-LABEL: 'rotl_i64_3rd_arg_const'
; RV64-NEXT:  Cost Model: Found costs of 3 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_const'
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:6 CodeSize:3 Lat:3 SizeLat:3 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_const'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
  %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
  ret i64 %r
}

define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
; RV32-LABEL: 'rotl_i64_3rd_arg_var'
; RV32-NEXT:  Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64-LABEL: 'rotl_i64_3rd_arg_var'
; RV64-NEXT:  Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_var'
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_var'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
  %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
  ret i64 %r
}

define i32 @rotr_i32_3rd_arg_const(i32 %a) {
; RV32-LABEL: 'rotr_i32_3rd_arg_const'
; RV32-NEXT:  Cost Model: Found costs of 3 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64-LABEL: 'rotr_i32_3rd_arg_const'
; RV64-NEXT:  Cost Model: Found costs of 3 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_const'
; RV32ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_const'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
  %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
  ret i32 %r
}

define i32 @rotr_i32_3rd_arg_var(i32 %a, i32 %c) {
; RV32-LABEL: 'rotr_i32_3rd_arg_var'
; RV32-NEXT:  Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64-LABEL: 'rotr_i32_3rd_arg_var'
; RV64-NEXT:  Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_var'
; RV32ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_var'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
  %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
  ret i32 %r
}

define i64 @rotr_i64_3rd_arg_const(i64 %a) {
; RV32-LABEL: 'rotr_i64_3rd_arg_const'
; RV32-NEXT:  Cost Model: Found costs of RThru:6 CodeSize:3 Lat:3 SizeLat:3 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64-LABEL: 'rotr_i64_3rd_arg_const'
; RV64-NEXT:  Cost Model: Found costs of 3 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_const'
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:6 CodeSize:3 Lat:3 SizeLat:3 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_const'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
  %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
  ret i64 %r
}

define i64 @rotr_i64_3rd_arg_var(i64 %a, i64 %c) {
; RV32-LABEL: 'rotr_i64_3rd_arg_var'
; RV32-NEXT:  Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
; RV32-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64-LABEL: 'rotr_i64_3rd_arg_var'
; RV64-NEXT:  Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
; RV64-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_var'
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
; RV32ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_var'
; RV64ZBB-NEXT:  Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
; RV64ZBB-NEXT:  Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
  %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
  ret i64 %r
}