# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s

...
---
name:            test_uavgfloor_i16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: test_uavgfloor_i16
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %w0_copy:_(s32) = COPY $w0
    ; CHECK-NEXT: %w1_copy:_(s32) = COPY $w1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC %w0_copy(s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC %w1_copy(s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[ZEXT1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
    ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %w0_copy:_(s32) = COPY $w0
    %w1_copy:_(s32) = COPY $w1

    %0:_(s16) = G_TRUNC %w0_copy(s32)
    %1:_(s16) = G_TRUNC %w1_copy(s32)

    %2:_(s32) = G_ZEXT %0(s16)
    %3:_(s32) = G_ZEXT %1(s16)

    %4:_(s32) = G_ADD %2, %3

    %5:_(s32) = G_CONSTANT i32 1
    %6:_(s32) = G_LSHR %4, %5(s32)

    %7:_(s16) = G_TRUNC %6(s32)

    %ret_ext:_(s32) = G_ANYEXT %7(s16)
    $w0 = COPY %ret_ext(s32)
    RET_ReallyLR implicit $w0

...
---
name:            test_uavgfloor_v8s16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: test_uavgfloor_v8s16
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK-NEXT: [[UAVGFLOOR:%[0-9]+]]:_(<8 x s16>) = G_UAVGFLOOR [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $q0 = COPY [[UAVGFLOOR]](<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1

    %ext0:_(<8 x s32>) = G_ZEXT %0
    %ext1:_(<8 x s32>) = G_ZEXT %1

    %sum:_(<8 x s32>) = G_ADD %ext0, %ext1

    %shift_cst:_(s32) = G_CONSTANT i32 1
    %v_shift_cst:_(<8 x s32>) = G_BUILD_VECTOR %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst
    %shift:_(<8 x s32>) = G_LSHR %sum, %v_shift_cst

    %res:_(<8 x s16>) = G_TRUNC %shift
    $q0 = COPY %res
    RET_ReallyLR implicit $q0

...
---
name:            test_savgfloor_i16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: test_savgfloor_i16
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %w0_copy:_(s32) = COPY $w0
    ; CHECK-NEXT: %w1_copy:_(s32) = COPY $w1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %w0_copy, 16
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %w1_copy, 16
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
    ; CHECK-NEXT: $w0 = COPY [[ASHR]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %w0_copy:_(s32) = COPY $w0
    %w1_copy:_(s32) = COPY $w1

    %0:_(s16) = G_TRUNC %w0_copy(s32)
    %1:_(s16) = G_TRUNC %w1_copy(s32)

    %2:_(s32) = G_SEXT %0(s16)
    %3:_(s32) = G_SEXT %1(s16)

    %4:_(s32) = G_ADD %2, %3

    %5:_(s32) = G_CONSTANT i32 1
    %6:_(s32) = G_ASHR %4, %5(s32)

    %7:_(s16) = G_TRUNC %6(s32)

    %ret_ext:_(s32) = G_ANYEXT %7(s16)
    $w0 = COPY %ret_ext(s32)
    RET_ReallyLR implicit $w0

...
---
name:            test_savgfloor_v8s16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: test_savgfloor_v8s16
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK-NEXT: [[SAVGFLOOR:%[0-9]+]]:_(<8 x s16>) = G_SAVGFLOOR [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $q0 = COPY [[SAVGFLOOR]](<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1

    %ext0:_(<8 x s32>) = G_SEXT %0
    %ext1:_(<8 x s32>) = G_SEXT %1

    %sum:_(<8 x s32>) = G_ADD %ext0, %ext1

    %shift_cst:_(s32) = G_CONSTANT i32 1
    %v_shift_cst:_(<8 x s32>) = G_BUILD_VECTOR %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst
    %shift:_(<8 x s32>) = G_ASHR %sum, %v_shift_cst

    %res:_(<8 x s16>) = G_TRUNC %shift
    $q0 = COPY %res
    RET_ReallyLR implicit $q0

...
---
name:            test_negative_floor
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: test_negative_floor
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %w0_copy:_(s32) = COPY $w0
    ; CHECK-NEXT: %w1_copy:_(s32) = COPY $w1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC %w0_copy(s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC %w1_copy(s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[ZEXT1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
    ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %w0_copy:_(s32) = COPY $w0
    %w1_copy:_(s32) = COPY $w1

    %0:_(s16) = G_TRUNC %w0_copy(s32)
    %1:_(s16) = G_TRUNC %w1_copy(s32)

    %2:_(s32) = G_ZEXT %0(s16)
    %3:_(s32) = G_ZEXT %1(s16)

    %4:_(s32) = G_ADD %2, %3

    %5:_(s32) = G_CONSTANT i32 2
    %6:_(s32) = G_LSHR %4, %5(s32)

    %7:_(s16) = G_TRUNC %6(s32)

    %ret_ext:_(s32) = G_ANYEXT %7(s16)
    $w0 = COPY %ret_ext(s32)
    RET_ReallyLR implicit $w0

...
---
name:            test_uavgceil_s32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: test_uavgceil_s32
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %w0_copy:_(s32) = COPY $w0
    ; CHECK-NEXT: %w1_copy:_(s32) = COPY $w1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC %w0_copy(s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC %w1_copy(s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16)
    ; CHECK-NEXT: %sum:_(s32) = G_ADD [[ZEXT]], [[ZEXT1]]
    ; CHECK-NEXT: %cst1:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %add_one:_(s32) = G_ADD %sum, %cst1
    ; CHECK-NEXT: %cst_shift:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %res:_(s32) = G_LSHR %add_one, %cst_shift(s32)
    ; CHECK-NEXT: $w0 = COPY %res(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %w0_copy:_(s32) = COPY $w0
    %w1_copy:_(s32) = COPY $w1
    %0:_(s16) = G_TRUNC %w0_copy(s32)
    %1:_(s16) = G_TRUNC %w1_copy(s32)
    %2:_(s32) = G_ZEXT %0(s16)
    %3:_(s32) = G_ZEXT %1(s16)

    %sum:_(s32) = G_ADD %2, %3
    %cst1:_(s32) = G_CONSTANT i32 1
    %add_one:_(s32) = G_ADD %sum, %cst1
    %cst_shift:_(s32) = G_CONSTANT i32 1
    %res:_(s32) = G_LSHR %add_one, %cst_shift

    $w0 = COPY %res(s32)
    RET_ReallyLR implicit $w0

...
---
name:            test_savgceil_s32_associative
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: test_savgceil_s32_associative
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %w0_copy:_(s32) = COPY $w0
    ; CHECK-NEXT: %w1_copy:_(s32) = COPY $w1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %w0_copy, 16
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %w1_copy, 16
    ; CHECK-NEXT: %cst1:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
    ; CHECK-NEXT: %sum:_(s32) = G_ADD [[ADD]], %cst1
    ; CHECK-NEXT: %cst_shift:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %res:_(s32) = G_ASHR %sum, %cst_shift(s32)
    ; CHECK-NEXT: $w0 = COPY %res(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %w0_copy:_(s32) = COPY $w0
    %w1_copy:_(s32) = COPY $w1
    %0:_(s16) = G_TRUNC %w0_copy(s32)
    %1:_(s16) = G_TRUNC %w1_copy(s32)
    %2:_(s32) = G_SEXT %0(s16)
    %3:_(s32) = G_SEXT %1(s16)

    %cst1:_(s32) = G_CONSTANT i32 1
    %add_one:_(s32) = G_ADD %2, %cst1
    %sum:_(s32) = G_ADD %add_one, %3
    %cst_shift:_(s32) = G_CONSTANT i32 1
    %res:_(s32) = G_ASHR %sum, %cst_shift

    $w0 = COPY %res(s32)
    RET_ReallyLR implicit $w0

...
---
name:            test_uavgceil_v8s16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: test_uavgceil_v8s16
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK-NEXT: [[UAVGCEIL:%[0-9]+]]:_(<8 x s16>) = G_UAVGCEIL [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $q0 = COPY [[UAVGCEIL]](<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %ext0:_(<8 x s32>) = G_ZEXT %0
    %ext1:_(<8 x s32>) = G_ZEXT %1
    %sum:_(<8 x s32>) = G_ADD %ext0, %ext1
    %cst1:_(s32) = G_CONSTANT i32 1
    %v_cst1:_(<8 x s32>) = G_BUILD_VECTOR %cst1, %cst1, %cst1, %cst1, %cst1, %cst1, %cst1, %cst1
    %add_one:_(<8 x s32>) = G_ADD %sum, %v_cst1
    %shift_cst:_(s32) = G_CONSTANT i32 1
    %v_shift_cst:_(<8 x s32>) = G_BUILD_VECTOR %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst, %shift_cst
    %shift:_(<8 x s32>) = G_LSHR %add_one, %v_shift_cst
    %res:_(<8 x s16>) = G_TRUNC %shift
    $q0 = COPY %res
    RET_ReallyLR implicit $q0

...
---
name:            test_negative_ceil_bad_constant
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: test_negative_ceil_bad_constant
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %w0_copy:_(s32) = COPY $w0
    ; CHECK-NEXT: %w1_copy:_(s32) = COPY $w1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC %w0_copy(s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC %w1_copy(s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16)
    ; CHECK-NEXT: %sum:_(s32) = G_ADD [[ZEXT]], [[ZEXT1]]
    ; CHECK-NEXT: %cst2:_(s32) = G_CONSTANT i32 2
    ; CHECK-NEXT: %add_two:_(s32) = G_ADD %sum, %cst2
    ; CHECK-NEXT: %cst_shift:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %res:_(s32) = G_LSHR %add_two, %cst_shift(s32)
    ; CHECK-NEXT: $w0 = COPY %res(s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %w0_copy:_(s32) = COPY $w0
    %w1_copy:_(s32) = COPY $w1
    %0:_(s16) = G_TRUNC %w0_copy(s32)
    %1:_(s16) = G_TRUNC %w1_copy(s32)
    %2:_(s32) = G_ZEXT %0(s16)
    %3:_(s32) = G_ZEXT %1(s16)
    %sum:_(s32) = G_ADD %2, %3
    %cst2:_(s32) = G_CONSTANT i32 2
    %add_two:_(s32) = G_ADD %sum, %cst2
    %cst_shift:_(s32) = G_CONSTANT i32 1
    %res:_(s32) = G_LSHR %add_two, %cst_shift
    $w0 = COPY %res(s32)
    RET_ReallyLR implicit $w0