# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "arm64-apple-darwin"

  define void @test_memcpy1(ptr nocapture %dst, ptr nocapture readonly %src, i64 %len) local_unnamed_addr #0 {
  entry:
    %0 = bitcast ptr %dst to ptr
    %1 = bitcast ptr %src to ptr
    tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 %len, i1 false)
    ret void
  }

  declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg) #1
  declare void @llvm.memcpy.p1.p2.i64(ptr addrspace(1) nocapture writeonly, ptr addrspace(2) nocapture readonly, i64, i1 immarg) #1

  define void @test_memcpy2_const(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr #0 {
  entry:
    %0 = bitcast ptr %dst to ptr
    %1 = bitcast ptr %src to ptr
    tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 72, i1 false)
    ret void
  }

  define void @test_memcpy2_const_optsize(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr #2 {
  entry:
    %0 = bitcast ptr %dst to ptr
    %1 = bitcast ptr %src to ptr
    tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 72, i1 false)
    ret void
  }

  define void @test_memcpy2_const_minsize(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr #3 {
  entry:
    %0 = bitcast ptr %dst to ptr
    %1 = bitcast ptr %src to ptr
    tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 72, i1 false)
    ret void
  }

  define void @test_memcpy3_const_arrays_unaligned(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr #0 {
  entry:
    %0 = bitcast ptr %dst to ptr
    %1 = bitcast ptr %src to ptr
    tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 143, i1 false)
    ret void
  }

  define void @test_memcpy_addrspace(ptr addrspace(1) nocapture %dst, ptr addrspace(2) nocapture readonly %src) local_unnamed_addr #0 {
  entry:
    %0 = bitcast ptr addrspace(1) %dst to ptr addrspace(1)
    %1 = bitcast ptr addrspace(2) %src to ptr addrspace(2)
    tail call void @llvm.memcpy.p1.p2.i64(ptr addrspace(1) align 4 %0, ptr addrspace(2) align 4 %1, i64 72, i1 false)
    ret void
  }


  attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2" "use-soft-float"="false" }
  attributes #1 = { argmemonly nounwind }
  attributes #2 = { optsize }
  attributes #3 = { minsize }

...
---
name:            test_memcpy1
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $x0, $x1, $x2

    ; CHECK-LABEL: name: test_memcpy1
    ; CHECK: liveins: $x0, $x1, $x2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
    ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(p0) = COPY $x0
    %1:_(p0) = COPY $x1
    %2:_(s64) = COPY $x2
    G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    RET_ReallyLR

...
---
name:            test_memcpy2_const
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test_memcpy2_const
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
    ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
    ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
    ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
    ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
    ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
    ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
    ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
    ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD4]](i64), [[PTR_ADD7]](p0) :: (store (s64) into %ir.0 + 64, align 4)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(p0) = COPY $x0
    %1:_(p0) = COPY $x1
    %2:_(s64) = G_CONSTANT i64 72
    G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    RET_ReallyLR

...
---
name:            test_memcpy2_const_optsize
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test_memcpy2_const_optsize
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
    ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
    ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
    ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
    ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
    ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
    ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
    ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
    ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD4]](i64), [[PTR_ADD7]](p0) :: (store (s64) into %ir.0 + 64, align 4)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(p0) = COPY $x0
    %1:_(p0) = COPY $x1
    %2:_(s64) = G_CONSTANT i64 72
    G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    RET_ReallyLR

...
---
name:            test_memcpy2_const_minsize
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test_memcpy2_const_minsize
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72
    ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[C]](s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(p0) = COPY $x0
    %1:_(p0) = COPY $x1
    %2:_(s64) = G_CONSTANT i64 72
    G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    RET_ReallyLR

...
---
name:            test_memcpy3_const_arrays_unaligned
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test_memcpy3_const_arrays_unaligned
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
    ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
    ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
    ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
    ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
    ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
    ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
    ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
    ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 80
    ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](i64)
    ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
    ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 96
    ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](i64)
    ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
    ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 112
    ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](i64)
    ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
    ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 127
    ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](i64)
    ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
    ; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(p0) = COPY $x0
    %1:_(p0) = COPY $x1
    %2:_(s64) = G_CONSTANT i64 143
    G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
    RET_ReallyLR

...
---
name:            test_memcpy_addrspace
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: test_memcpy_addrspace
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
    ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
    ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
    ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
    ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p2) :: (load (s128) from %ir.1 + 48, align 4, addrspace 2)
    ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p1) :: (store (s128) into %ir.0 + 48, align 4, addrspace 1)
    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
    ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
    ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p2) :: (load (s64) from %ir.1 + 64, align 4, addrspace 2)
    ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
    ; CHECK-NEXT: G_STORE [[LOAD4]](i64), [[PTR_ADD7]](p1) :: (store (s64) into %ir.0 + 64, align 4, addrspace 1)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(p1) = COPY $x0
    %1:_(p2) = COPY $x1
    %2:_(s64) = G_CONSTANT i64 72
    G_MEMCPY %0(p1), %1(p2), %2(s64), 1 :: (store (s8) into %ir.0, align 4, addrspace 1), (load (s8) from %ir.1, align 4, addrspace 2)
    RET_ReallyLR


...