# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.

...
---
name:            DUPv4i32gpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv4i32gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr128 = DUPv4i32gpr %copy
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:gpr(i32) = COPY $w0
    %dup:fpr(<4 x i32>) = G_DUP %copy(i32)
    $q0 = COPY %dup(<4 x i32>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i64gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: DUPv2i64gpr
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr64 = COPY $x0
    ; CHECK-NEXT: %dup:fpr128 = DUPv2i64gpr %copy
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:gpr(i64) = COPY $x0
    %dup:fpr(<2 x i64>) = G_DUP %copy(i64)
    $q0 = COPY %dup(<2 x i64>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i32gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv2i32gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr64 = DUPv2i32gpr %copy
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:gpr(i32) = COPY $w0
    %dup:fpr(<2 x i32>) = G_DUP %copy(i32)
    $d0 = COPY %dup(<2 x i32>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv4i32lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $s0

    ; CHECK-LABEL: name: DUPv4i32lane
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:fpr32 = COPY $s0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
    ; CHECK-NEXT: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:fpr(i32) = COPY $s0
    %dup:fpr(<4 x i32>) = G_DUP %copy(i32)
    $q0 = COPY %dup(<4 x i32>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i64lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $d0
    ; CHECK-LABEL: name: DUPv2i64lane
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:fpr64 = COPY $d0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub
    ; CHECK-NEXT: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:fpr(i64) = COPY $d0
    %dup:fpr(<2 x i64>) = G_DUP %copy(i64)
    $q0 = COPY %dup(<2 x i64>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i32lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $s0
    ; CHECK-LABEL: name: DUPv2i32lane
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:fpr32 = COPY $s0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
    ; CHECK-NEXT: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:fpr(i32) = COPY $s0
    %dup:fpr(<2 x i32>) = G_DUP %copy(i32)
    $d0 = COPY %dup(<2 x i32>)
    RET_ReallyLR implicit $d0


...
---
name:            DUPv4i16lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $h0
    ; CHECK-LABEL: name: DUPv4i16lane
    ; CHECK: liveins: $h0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:fpr16 = COPY $h0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
    ; CHECK-NEXT: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:fpr(i16) = COPY $h0
    %dup:fpr(<4 x i16>) = G_DUP %copy(i16)
    $d0 = COPY %dup(<4 x i16>)
    RET_ReallyLR implicit $d0
...
---
name:            DUPv4i16gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv4i16gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:gpr(i32) = COPY $w0
    %dup:fpr(<4 x i16>) = G_DUP %copy(i32)
    $d0 = COPY %dup(<4 x i16>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv8i16lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $h0
    ; CHECK-LABEL: name: DUPv8i16lane
    ; CHECK: liveins: $h0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:fpr16 = COPY $h0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
    ; CHECK-NEXT: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:fpr(i16) = COPY $h0
    %dup:fpr(<8 x i16>) = G_DUP %copy(i16)
    $q0 = COPY %dup(<8 x i16>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv8i16gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv8i16gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:gpr(i32) = COPY $w0
    %dup:fpr(<8 x i16>) = G_DUP %copy(i32)
    $q0 = COPY %dup(<8 x i16>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv8i16gpr_s16_src
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv8i16gpr_s16_src
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:gpr(i32) = COPY $w0
    %trunc:gpr(i16) = G_TRUNC %copy
    %dup:fpr(<8 x i16>) = G_DUP %trunc(i16)
    $q0 = COPY %dup(<8 x i16>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv4s16gpr_s16_src
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv4s16gpr_s16_src
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:gpr(i32) = COPY $w0
    %trunc:gpr(i16) = G_TRUNC %copy
    %dup:fpr(<4 x i16>) = G_DUP %trunc(i16)
    $d0 = COPY %dup(<4 x i16>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv8i8gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv8i8gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:gpr(i32) = COPY $w0
    %dup:fpr(<8 x i8>) = G_DUP %copy(i32)
    $d0 = COPY %dup(<8 x i8>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv8i8gpr_s8_src
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv8i8gpr_s8_src
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %copy:gpr(i32) = COPY $w0
    %trunc:gpr(i8) = G_TRUNC %copy(i32)
    %dup:fpr(<8 x i8>) = G_DUP %trunc(i8)
    $d0 = COPY %dup(<8 x i8>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv16i8gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv16i8gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:gpr(i32) = COPY $w0
    %dup:fpr(<16 x i8>) = G_DUP %copy(i32)
    $q0 = COPY %dup(<16 x i8>)
    RET_ReallyLR implicit $q0
...
---
name:            DUPv16i8gpr_s8_src
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv16i8gpr_s8_src
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:gpr32 = COPY $w0
    ; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %copy:gpr(i32) = COPY $w0
    %trunc:gpr(i8) = G_TRUNC %copy
    %dup:fpr(<16 x i8>) = G_DUP %trunc(i8)
    $q0 = COPY %dup(<16 x i8>)
    RET_ReallyLR implicit $q0
...
---
name:            dup_v2p0
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: dup_v2p0
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
    ; CHECK-NEXT: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]]
    ; CHECK-NEXT: $q0 = COPY [[DUPv2i64gpr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:gpr(p0) = COPY $x0
    %4:fpr(<2 x p0>) = G_DUP %0(p0)
    $q0 = COPY %4(<2 x p0>)
    RET_ReallyLR implicit $q0

...
---
name:            cst_v4s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: cst_v4s32
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %dup:fpr128 = MOVIv4i32 3, 0
    ; CHECK-NEXT: $q0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %cst:gpr(i32) = G_CONSTANT i32 3
    %dup:fpr(<4 x i32>) = G_DUP %cst(i32)
    $q0 = COPY %dup(<4 x i32>)
    RET_ReallyLR implicit $q0

...
---
name:            cst_v8s8
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: cst_v8s8
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %dup:fpr64 = MOVIv8b_ns 3
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %cst:gpr(i8) = G_CONSTANT i8 3
    %dup:fpr(<8 x i8>) = G_DUP %cst(i8)
    $d0 = COPY %dup(<8 x i8>)
    RET_ReallyLR implicit $d0
...
---
name:            cst_v2p0
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: cst_v2p0
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
    ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
    ; CHECK-NEXT: $q0 = COPY [[LDRQui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %cst:gpr(p0) = G_CONSTANT i64 3
    %dup:fpr(<2 x p0>) = G_DUP %cst(p0)
    $q0 = COPY %dup(<2 x p0>)
    RET_ReallyLR implicit $q0
...
---
name:            cstv4i16gpri32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins:
    ; CHECK-LABEL: name: cstv4i16gpri32
    ; CHECK: %dup:fpr64 = MOVIv4i16 3, 0
    ; CHECK-NEXT: $d0 = COPY %dup
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %cst:gpr(i32) = G_CONSTANT i32 3
    %dup:fpr(<4 x i16>) = G_DUP %cst(i32)
    $d0 = COPY %dup(<4 x i16>)
    RET_ReallyLR implicit $d0

...