# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s

...
---
name:            load_s8_s16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s8_s16
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub
    ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
    $h0 = COPY %2(s16)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s8_s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s8_s32
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub
    ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
    $s0 = COPY %2(s32)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s8_s64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s8_s64
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub
    ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
    $d0 = COPY %2(s64)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s16_s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s16_s32
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub
    ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))
    $s0 = COPY %2(s32)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s16_s64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s16_s64
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub
    ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))
    $d0 = COPY %2(s64)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s32_s64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s32_s64
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (s32))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub
    ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s32))
    $d0 = COPY %2(s64)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s8_s16_pre
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s8_s16_pre
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub
    ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
    $h0 = COPY %2(s16)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s8_s32_pre
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s8_s32_pre
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub
    ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
    $s0 = COPY %2(s32)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s8_s64_pre
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s8_s64_pre
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub
    ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
    $d0 = COPY %2(s64)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s16_s32_pre
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s16_s32_pre
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub
    ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))
    $s0 = COPY %2(s32)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s16_s64_pre
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s16_s64_pre
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub
    ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))
    $d0 = COPY %2(s64)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...
---
name:            load_s32_s64_pre
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x0
    ; CHECK-LABEL: name: load_s32_s64_pre
    ; CHECK: liveins: $d0, $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (s32))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub
    ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: $x0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 4
    %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s32))
    $d0 = COPY %2(s64)
    $x0 = COPY %3(p0)
    RET_ReallyLR implicit $d0

...