# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s ... --- name: test_f16.rint alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true machineFunctionInfo: {} body: | bb.0: liveins: $h0 ; CHECK-LABEL: name: test_f16.rint ; CHECK: liveins: $h0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr ; CHECK-NEXT: $h0 = COPY [[FCVTHSr]] ; CHECK-NEXT: RET_ReallyLR implicit $h0 %0:fpr(f16) = COPY $h0 %2:fpr(f32) = G_FPEXT %0(f16) %3:fpr(f32) = G_FRINT %2 %1:fpr(f16) = G_FPTRUNC %3(f32) $h0 = COPY %1(f16) RET_ReallyLR implicit $h0 ... --- name: test_v4f16.rint alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true machineFunctionInfo: {} body: | bb.0: liveins: $d0 ; CHECK-LABEL: name: test_v4f16.rint ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3 ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr1]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr1]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr2]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr2]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr3]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr3]], implicit $fpcr ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub ; CHECK-NEXT: $d0 = COPY [[COPY2]] ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(<4 x f16>) = COPY $d0 %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16) = G_UNMERGE_VALUES %0(<4 x f16>) %16:fpr(f32) = G_FPEXT %2(f16) %17:fpr(f32) = G_FRINT %16 %6:fpr(f16) = G_FPTRUNC %17(f32) %14:fpr(f32) = G_FPEXT %3(f16) %15:fpr(f32) = G_FRINT %14 %7:fpr(f16) = G_FPTRUNC %15(f32) %12:fpr(f32) = G_FPEXT %4(f16) %13:fpr(f32) = G_FRINT %12 %8:fpr(f16) = G_FPTRUNC %13(f32) %10:fpr(f32) = G_FPEXT %5(f16) %11:fpr(f32) = G_FRINT %10 %9:fpr(f16) = G_FPTRUNC %11(f32) %1:fpr(<4 x f16>) = G_BUILD_VECTOR %6(f16), %7(f16), %8(f16), %9(f16) $d0 = COPY %1(<4 x f16>) RET_ReallyLR implicit $d0 ... --- name: test_v8f16.rint alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true machineFunctionInfo: {} body: | bb.0: liveins: $q0 ; CHECK-LABEL: name: test_v8f16.rint ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3 ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4 ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5 ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6 ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7 ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr1]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr1]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr2]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr2]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr3]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr3]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr4:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr4:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr4]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr4:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr4]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr5:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr5:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr5]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr5:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr5]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr6:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr6:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr6]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr6:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr6]], implicit $fpcr ; CHECK-NEXT: [[FCVTSHr7:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]], implicit $fpcr ; CHECK-NEXT: [[FRINTXSr7:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr7]], implicit $fpcr ; CHECK-NEXT: [[FCVTHSr7:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr7]], implicit $fpcr ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0 ; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub ; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0 ; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]] ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(<8 x f16>) = COPY $q0 %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16), %6:fpr(f16), %7:fpr(f16), %8:fpr(f16), %9:fpr(f16) = G_UNMERGE_VALUES %0(<8 x s16>) %32:fpr(f32) = G_FPEXT %2(f16) %33:fpr(f32) = G_FRINT %32 %10:fpr(f16) = G_FPTRUNC %33(f32) %30:fpr(f32) = G_FPEXT %3(f16) %31:fpr(f32) = G_FRINT %30 %11:fpr(f16) = G_FPTRUNC %31(f32) %28:fpr(f32) = G_FPEXT %4(f16) %29:fpr(f32) = G_FRINT %28 %12:fpr(f16) = G_FPTRUNC %29(f32) %26:fpr(f32) = G_FPEXT %5(f16) %27:fpr(f32) = G_FRINT %26 %13:fpr(f16) = G_FPTRUNC %27(f32) %24:fpr(f32) = G_FPEXT %6(f16) %25:fpr(f32) = G_FRINT %24 %14:fpr(f16) = G_FPTRUNC %25(f32) %22:fpr(f32) = G_FPEXT %7(f16) %23:fpr(f32) = G_FRINT %22 %15:fpr(f16) = G_FPTRUNC %23(f32) %20:fpr(f32) = G_FPEXT %8(f16) %21:fpr(f32) = G_FRINT %20 %16:fpr(f16) = G_FPTRUNC %21(f32) %18:fpr(f32) = G_FPEXT %9(f16) %19:fpr(f32) = G_FRINT %18 %17:fpr(f16) = G_FPTRUNC %19(f32) %1:fpr(<8 x f16>) = G_BUILD_VECTOR %10(f16), %11(f16), %12(f16), %13(f16), %14(f16), %15(f16), %16(f16), %17(f16) $q0 = COPY %1(<8 x f16>) RET_ReallyLR implicit $q0