# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  define void @test_store_i8(i32, i8 %val, ptr %addr) { ret void }
  define void @test_store_i16(i32, i16 %val, ptr %addr) { ret void }
  define void @test_store_i32(i32, i32 %val, ptr %addr) { ret void }
  define void @test_store_i64(i32, i64 %val, ptr %addr) { ret void }
...
---
name:            test_store_i8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1, $x2

    ; CHECK-LABEL: name: test_store_i8
    ; CHECK: liveins: $w0, $w1, $x2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
    ; CHECK-NEXT: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
    ; CHECK-NEXT: $w0 = COPY %5
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %3:gpr(i32) = COPY $w1
    %2:gpr(p0) = COPY $x2
    %6:gpr(i64) = G_CONSTANT i64 255
    %7:gpr(i64) = G_ANYEXT %3(i32)
    %4:gpr(i64) = G_AND %7, %6
    %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (s8) into %ir.addr)
    $w0 = COPY %5(i32)
    RET_ReallyLR implicit $w0

...
---
name:            test_store_i16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1, $x2

    ; CHECK-LABEL: name: test_store_i16
    ; CHECK: liveins: $w0, $w1, $x2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
    ; CHECK-NEXT: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
    ; CHECK-NEXT: $w0 = COPY %5
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %3:gpr(i32) = COPY $w1
    %2:gpr(p0) = COPY $x2
    %6:gpr(i64) = G_CONSTANT i64 65535
    %7:gpr(i64) = G_ANYEXT %3(i32)
    %4:gpr(i64) = G_AND %7, %6
    %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (s16) into %ir.addr)
    $w0 = COPY %5(i32)
    RET_ReallyLR implicit $w0

...
---
name:            test_store_i32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1, $x2

    ; CHECK-LABEL: name: test_store_i32
    ; CHECK: liveins: $w0, $w1, $x2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
    ; CHECK-NEXT: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
    ; CHECK-NEXT: $w0 = COPY %3
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:gpr(i32) = COPY $w1
    %2:gpr(p0) = COPY $x2
    %3:gpr(i64) = G_ZEXT %1(i32)
    %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(i64), %2(p0) :: (volatile store (s32) into %ir.addr)
    $w0 = COPY %4(i32)
    RET_ReallyLR implicit $w0

...
---
name:            test_store_i64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $x1, $x2

    ; CHECK-LABEL: name: test_store_i64
    ; CHECK: liveins: $w0, $x1, $x2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
    ; CHECK-NEXT: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
    ; CHECK-NEXT: $w0 = COPY %2
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:gpr(i64) = COPY $x1
    %2:gpr(p0) = COPY $x2
    %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(i64), %2(p0) :: (volatile store (s64) into %ir.addr)
    $w0 = COPY %3(i32)
    RET_ReallyLR implicit $w0

...