; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define void @test_sqrshl_s32(float noundef %a, ptr %dst){
; CHECK-LABEL: test_sqrshl_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqrshl s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqrshl.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqrshl_s64(float noundef %a, ptr %dst){
; CHECK-LABEL: test_sqrshl_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqrshl d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_sqshl_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqshl_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqshl s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqshl.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqshl_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqshl_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqshl d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_uqrshl_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqrshl_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    uqrshl s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.uqrshl.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_uqrshl_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqrshl_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    uqrshl d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_uqshl_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqshl_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    uqshl s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.uqshl.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_uqshl_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqshl_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    uqshl d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_sqshrn_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqshrn_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqshrn s0, d0, #1
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqshrn.i32(i64 %cvt, i32 1)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqshrun_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqshrun_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqshrun s0, d0, #1
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqshrun.i32(i64 %cvt, i32 1)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_uqshrn_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqshrn_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    uqshrn s0, d0, #1
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.uqshrn.i32(i64 %cvt, i32 1)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqrshrn_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqrshrn_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqrshrn s0, d0, #1
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqrshrn.i32(i64 %cvt, i32 1)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqrshrun_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqrshrun_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqrshrun s0, d0, #1
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 %cvt, i32 1)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_uqrshrn_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqrshrn_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    uqrshrn s0, d0, #1
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 %cvt, i32 1)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_suqadd_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_suqadd_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    suqadd s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.suqadd.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_suqadd_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_suqadd_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    suqadd d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.suqadd.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_usqadd_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_usqadd_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.usqadd.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_usqadd_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_usqadd_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.usqadd.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_sqadd_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqadd_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqadd s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqadd_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqadd_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqadd d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_sqsub_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqsub_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqsub s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqsub_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqsub_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqsub d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_uqadd_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqadd_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    uqadd s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_uqadd_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqadd_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    uqadd d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_abs_s64(float noundef %a, ptr %dst) {
; CHECK-SD-LABEL: test_abs_s64:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    fcvtzs d0, s0
; CHECK-SD-NEXT:    abs d0, d0
; CHECK-SD-NEXT:    str d0, [x0]
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: test_abs_s64:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvtzs x8, s0
; CHECK-GI-NEXT:    cmp x8, #0
; CHECK-GI-NEXT:    cneg x8, x8, le
; CHECK-GI-NEXT:    str x8, [x0]
; CHECK-GI-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.abs.i64(i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_uqsub_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqsub_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    uqsub s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_uqsub_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_uqsub_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    uqsub d0, d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %cvt, i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_sqdmulls_scalar(float %A, ptr %dst){
; CHECK-LABEL: test_sqdmulls_scalar:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqdmull d0, s0, s0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %A)
  %prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32  %cvt, i32  %cvt)
  store i64 %prod, ptr %dst, align 8
  ret void
}

define void @test_sqdmulh_scalar(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqdmulh_scalar:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqdmulh s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst
  ret void
}

define void @test_sqrdmulh_scalar(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqrdmulh_scalar:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqrdmulh s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst
  ret void
}

define void @test_sqrdmlah_scalar(float noundef %a, ptr %dst) #0 {
; CHECK-LABEL: test_sqrdmlah_scalar:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqrdmlah s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = call i32 @llvm.aarch64.neon.sqrdmlah.i32(i32 %cvt, i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst
  ret void
}

define void @test_sqrdmlsh_scalar(float noundef %a, ptr %dst) #0 {
; CHECK-LABEL: test_sqrdmlsh_scalar:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqrdmlsh s0, s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = call i32 @llvm.aarch64.neon.sqrdmlsh.i32(i32 %cvt, i32 %cvt, i32 %cvt)
  store i32 %res, ptr %dst
  ret void
}

define void @test_sqabs_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqabs_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqabs s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqabs_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqabs_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqabs d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

define void @test_sqneg_s32(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqneg_s32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    sqneg s0, s0
; CHECK-NEXT:    str s0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
  %res = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %cvt)
  store i32 %res, ptr %dst, align 4
  ret void
}

define void @test_sqneg_s64(float noundef %a, ptr %dst) {
; CHECK-LABEL: test_sqneg_s64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    sqneg d0, d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  %cvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %a)
  %res = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %cvt)
  store i64 %res, ptr %dst, align 8
  ret void
}

attributes #0 = { "target-features"="+rdm" }