; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; CodeGenPrepare is expected to form overflow intrinsics to improve DAG/isel. define i1 @usubo_ult_i64(i64 %x, i64 %y, ptr %p) nounwind { ; CHECK-LABEL: usubo_ult_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: subs x8, x0, x1 ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: str x8, [x2] ; CHECK-NEXT: ret %s = sub i64 %x, %y store i64 %s, ptr %p %ov = icmp ult i64 %x, %y ret i1 %ov } ; Verify insertion point for single-BB. Toggle predicate. define i1 @usubo_ugt_i32(i32 %x, i32 %y, ptr %p) nounwind { ; CHECK-LABEL: usubo_ugt_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: subs w8, w0, w1 ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: ret %ov = icmp ugt i32 %y, %x %s = sub i32 %x, %y store i32 %s, ptr %p ret i1 %ov } ; Constant operand should match. define i1 @usubo_ugt_constant_op0_i8(i8 %x, ptr %p) nounwind { ; CHECK-LABEL: usubo_ugt_constant_op0_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: mov w9, #42 // =0x2a ; CHECK-NEXT: cmp w8, #42 ; CHECK-NEXT: sub w9, w9, w0 ; CHECK-NEXT: cset w8, hi ; CHECK-NEXT: strb w9, [x1] ; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: ret %s = sub i8 42, %x %ov = icmp ugt i8 %x, 42 store i8 %s, ptr %p ret i1 %ov } ; Compare with constant operand 0 is canonicalized by commuting, but verify match for non-canonical form. define i1 @usubo_ult_constant_op0_i16(i16 %x, ptr %p) nounwind { ; CHECK-LABEL: usubo_ult_constant_op0_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: mov w9, #43 // =0x2b ; CHECK-NEXT: cmp w8, #43 ; CHECK-NEXT: sub w9, w9, w0 ; CHECK-NEXT: cset w8, hi ; CHECK-NEXT: strh w9, [x1] ; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: ret %s = sub i16 43, %x %ov = icmp ult i16 43, %x store i16 %s, ptr %p ret i1 %ov } ; Subtract with constant operand 1 is canonicalized to add. define i1 @usubo_ult_constant_op1_i16(i16 %x, ptr %p) nounwind { ; CHECK-LABEL: usubo_ult_constant_op1_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: sub w9, w0, #44 ; CHECK-NEXT: cmp w8, #44 ; CHECK-NEXT: strh w9, [x1] ; CHECK-NEXT: cset w8, lo ; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: ret %s = add i16 %x, -44 %ov = icmp ult i16 %x, 44 store i16 %s, ptr %p ret i1 %ov } define i1 @usubo_ugt_constant_op1_i8(i8 %x, ptr %p) nounwind { ; CHECK-LABEL: usubo_ugt_constant_op1_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: sub w9, w0, #45 ; CHECK-NEXT: cmp w8, #45 ; CHECK-NEXT: strb w9, [x1] ; CHECK-NEXT: cset w8, lo ; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: ret %ov = icmp ugt i8 45, %x %s = add i8 %x, -45 store i8 %s, ptr %p ret i1 %ov } ; Special-case: subtract 1 changes the compare predicate and constant. define i1 @usubo_eq_constant1_op1_i32(i32 %x, ptr %p) nounwind { ; CHECK-LABEL: usubo_eq_constant1_op1_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: sub w9, w0, #1 ; CHECK-NEXT: cset w8, eq ; CHECK-NEXT: str w9, [x1] ; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: ret %s = add i32 %x, -1 %ov = icmp eq i32 %x, 0 store i32 %s, ptr %p ret i1 %ov } ; Borrow chain: or(icmp ult X, Y, and(icmp eq X, Y, carry_in)) -> cmp + sbcs. ; See https://github.com/llvm/llvm-project/issues/106118. define i1 @subcarry_ult_2x64(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind { ; CHECK-LABEL: subcarry_ult_2x64: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp x0, x2 ; CHECK-NEXT: sbcs xzr, x1, x3 ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %b0 = icmp ult i64 %x0, %y0 %b1 = icmp ult i64 %x1, %y1 %e1 = icmp eq i64 %x1, %y1 %bp = and i1 %b0, %e1 %br = or i1 %b1, %bp ret i1 %br } ; Commuted eq operands: icmp eq Y, X instead of icmp eq X, Y. define i1 @subcarry_ult_2x64_commuted_eq(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind { ; CHECK-LABEL: subcarry_ult_2x64_commuted_eq: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp x0, x2 ; CHECK-NEXT: sbcs xzr, x1, x3 ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %b0 = icmp ult i64 %x0, %y0 %b1 = icmp ult i64 %x1, %y1 %e1 = icmp eq i64 %y1, %x1 %bp = and i1 %b0, %e1 %br = or i1 %b1, %bp ret i1 %br } define i1 @subcarry_ult_3x64(i64 %x0, i64 %x1, i64 %x2, i64 %y0, i64 %y1, i64 %y2) nounwind { ; CHECK-LABEL: subcarry_ult_3x64: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp x0, x3 ; CHECK-NEXT: sbcs xzr, x1, x4 ; CHECK-NEXT: sbcs xzr, x2, x5 ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %b0 = icmp ult i64 %x0, %y0 %b1 = icmp ult i64 %x1, %y1 %e1 = icmp eq i64 %x1, %y1 %bp1 = and i1 %b0, %e1 %br1 = or i1 %b1, %bp1 %b2 = icmp ult i64 %x2, %y2 %e2 = icmp eq i64 %x2, %y2 %bp2 = and i1 %br1, %e2 %br2 = or i1 %b2, %bp2 ret i1 %br2 } ; Unsigned less than of two 2x128 integers combined into a borrow chain. define i1 @subcarry_ult_2x128(i128 %x0, i128 %x1, i128 %y0, i128 %y1) nounwind { ; CHECK-LABEL: subcarry_ult_2x128: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp x0, x4 ; CHECK-NEXT: sbcs xzr, x1, x5 ; CHECK-NEXT: sbcs xzr, x2, x6 ; CHECK-NEXT: sbcs xzr, x3, x7 ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %b0 = icmp ult i128 %x0, %y0 %b1 = icmp ult i128 %x1, %y1 %e1 = icmp eq i128 %x1, %y1 %bp = and i1 %b0, %e1 %br = or i1 %b1, %bp ret i1 %br } ; Negative test: icmp eq compares different operands than icmp ult. define i1 @no_subcarry_different_ops(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind { ; CHECK-LABEL: no_subcarry_different_ops: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp x0, x2 ; CHECK-NEXT: ccmp x1, x0, #0, lo ; CHECK-NEXT: ccmp x1, x3, #0, ne ; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %b0 = icmp ult i64 %x0, %y0 %b1 = icmp ult i64 %x1, %y1 %e1 = icmp eq i64 %x1, %x0 %bp = and i1 %b0, %e1 %br = or i1 %b1, %bp ret i1 %br } ; Negative test: icmp slt instead of icmp ult. define i1 @no_subcarry_signed(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind { ; CHECK-LABEL: no_subcarry_signed: ; CHECK: // %bb.0: ; CHECK-NEXT: cmp x0, x2 ; CHECK-NEXT: cset w8, lo ; CHECK-NEXT: cmp x1, x3 ; CHECK-NEXT: csel w8, wzr, w8, ne ; CHECK-NEXT: csinc w0, w8, wzr, ge ; CHECK-NEXT: ret %b0 = icmp ult i64 %x0, %y0 %b1 = icmp slt i64 %x1, %y1 %e1 = icmp eq i64 %x1, %y1 %bp = and i1 %b0, %e1 %br = or i1 %b1, %bp ret i1 %br } ; Negative test: vector types are not a borrow chain. define <4 x i1> @no_subcarry_vector(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %y0, <4 x i32> %y1) nounwind { ; CHECK-LABEL: no_subcarry_vector: ; CHECK: // %bb.0: ; CHECK-NEXT: cmeq v4.4s, v1.4s, v3.4s ; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhi v1.4s, v3.4s, v1.4s ; CHECK-NEXT: and v0.16b, v0.16b, v4.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: ret %b0 = icmp ult <4 x i32> %x0, %y0 %b1 = icmp ult <4 x i32> %x1, %y1 %e1 = icmp eq <4 x i32> %x1, %y1 %bp = and <4 x i1> %b0, %e1 %br = or <4 x i1> %b1, %bp ret <4 x i1> %br } ; Verify insertion point for multi-BB. declare void @call(i1) define i1 @usubo_ult_sub_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) nounwind { ; CHECK-LABEL: usubo_ult_sub_dominates_i64: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: tbz w3, #0, .LBB14_2 ; CHECK-NEXT: // %bb.1: // %t ; CHECK-NEXT: subs x8, x0, x1 ; CHECK-NEXT: cset w3, lo ; CHECK-NEXT: str x8, [x2] ; CHECK-NEXT: .LBB14_2: // %common.ret ; CHECK-NEXT: and w0, w3, #0x1 ; CHECK-NEXT: ret entry: br i1 %cond, label %t, label %f t: %s = sub i64 %x, %y store i64 %s, ptr %p br i1 %cond, label %end, label %f f: ret i1 %cond end: %ov = icmp ult i64 %x, %y ret i1 %ov } define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) nounwind { ; CHECK-LABEL: usubo_ult_cmp_dominates_i64: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: mov w19, w3 ; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: tbz w3, #0, .LBB15_3 ; CHECK-NEXT: // %bb.1: // %t ; CHECK-NEXT: cmp x0, x1 ; CHECK-NEXT: mov x22, x0 ; CHECK-NEXT: mov x20, x2 ; CHECK-NEXT: cset w21, lo ; CHECK-NEXT: mov x23, x1 ; CHECK-NEXT: mov w0, w21 ; CHECK-NEXT: bl call ; CHECK-NEXT: subs x8, x22, x23 ; CHECK-NEXT: b.hs .LBB15_3 ; CHECK-NEXT: // %bb.2: // %end ; CHECK-NEXT: mov w19, w21 ; CHECK-NEXT: str x8, [x20] ; CHECK-NEXT: .LBB15_3: // %common.ret ; CHECK-NEXT: and w0, w19, #0x1 ; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x23, [sp], #48 // 16-byte Folded Reload ; CHECK-NEXT: ret entry: br i1 %cond, label %t, label %f t: %ov = icmp ult i64 %x, %y call void @call(i1 %ov) br i1 %ov, label %end, label %f f: ret i1 %cond end: %s = sub i64 %x, %y store i64 %s, ptr %p ret i1 %ov }