# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=arm64-apple-ios -mattr +cmpbr -run-pass=early-ifcvt -verify-machineinstrs -simplify-mir -o - %s | FileCheck %s
---
name:            cb_diamond
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr64 }
  - { id: 1, class: gpr64 }
  - { id: 2, class: gpr64 }
  - { id: 3, class: gpr64 }
  - { id: 4, class: gpr64 }
  - { id: 5, class: gpr64 }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$x1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cb_diamond
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x0, $x1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
  ; CHECK-NEXT:   [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
  ; CHECK-NEXT:   $xzr = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[ADDXrr]], [[MADDXrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr killed [[CSELXr]], [[COPY]]
  ; CHECK-NEXT:   $x0 = COPY [[ADDXrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $x0, $x1

    %0:gpr64 = COPY $x0
    %1:gpr64 = COPY $x1
    CBXPrr 11, %0, %1, %bb.1
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr64 = ADDXrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr64 = MADDXrrr %0, %1, $xzr
    B %bb.3

  bb.3:
    %4:gpr64 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr64 = ADDXrr killed %4, %0
    $x0 = COPY %5
    RET_ReallyLR implicit $x0
...
---
name:            cb_triangle
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr64 }
  - { id: 1, class: gpr64 }
  - { id: 2, class: gpr64 }
  - { id: 3, class: gpr64 }
  - { id: 4, class: gpr64 }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$x1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cb_triangle
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x0, $x1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
  ; CHECK-NEXT:   [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   $xzr = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY1]], [[ADDXrr]], 10, implicit $nzcv
  ; CHECK-NEXT:   [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr killed [[CSELXr]], [[COPY]]
  ; CHECK-NEXT:   $x0 = COPY [[ADDXrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $x0, $x1

    %0:gpr64 = COPY $x0
    %1:gpr64 = COPY $x1
    CBXPrr 10, %0, %1, %bb.2

  bb.1:
    successors: %bb.2
    %2:gpr64 = ADDXrr %0, %1

  bb.2:
    %3:gpr64 = PHI %1, %bb.0, %2, %bb.1
    %4:gpr64 = ADDXrr killed %3, %0
    $x0 = COPY %4
    RET_ReallyLR implicit $x0
...
---
name:            cbb_diamond_no_ext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbb_diamond_no_ext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBBAssertExt 11, %0, %1, %bb.1, -1, -1
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name:            cbb_diamond_zext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbb_diamond_zext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   [[ANDWri:%[0-9]+]]:gpr32common = ANDWri [[COPY1]], 7
  ; CHECK-NEXT:   $wzr = SUBSWrx [[COPY]], [[ANDWri]], 0, implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBBAssertExt 11, %0, %1, %bb.1, 0, 0
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name:            cbb_diamond_sext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbb_diamond_sext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   [[SBFMWri:%[0-9]+]]:gpr32common = SBFMWri [[COPY1]], 0, 7
  ; CHECK-NEXT:   $wzr = SUBSWrx [[COPY]], [[SBFMWri]], 32, implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBBAssertExt 11, %0, %1, %bb.1, 4, 4
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name:            cbh_diamond_zext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbh_diamond_zext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   [[ANDWri:%[0-9]+]]:gpr32common = ANDWri [[COPY1]], 15
  ; CHECK-NEXT:   $wzr = SUBSWrx [[COPY]], [[ANDWri]], 8, implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBHAssertExt 11, %0, %1, %bb.1, 1, 1
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name:            cbh_diamond_sext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbh_diamond_sext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   [[SBFMWri:%[0-9]+]]:gpr32common = SBFMWri [[COPY1]], 0, 15
  ; CHECK-NEXT:   $wzr = SUBSWrx [[COPY]], [[SBFMWri]], 40, implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBHAssertExt 11, %0, %1, %bb.1, 5, 5
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name:            cbh_diamond_lhs_sext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbh_diamond_lhs_sext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   [[SBFMWri:%[0-9]+]]:gpr32common = SBFMWri [[COPY1]], 0, 15
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[SBFMWri]], implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBHAssertExt 11, %0, %1, %bb.1, 5, -1
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name:            cbh_diamond_rhs_sext
alignment:       4
tracksRegLiveness: true
noPhis:          false
isSSA:           true
noVRegs:         false
hasFakeUses:     false
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: cbh_diamond_rhs_sext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
  ; CHECK-NEXT:   $wzr = SUBSWrx [[COPY]], [[COPY1]], 40, implicit-def $nzcv
  ; CHECK-NEXT:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[ADDWrr]], [[MADDWrrr]], 11, implicit $nzcv
  ; CHECK-NEXT:   [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[CSELWr]], [[COPY]]
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $w0, $w1

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    CBHAssertExt 11, %0, %1, %bb.1, -1, 5
    B %bb.2

  bb.1:
    successors: %bb.3
    %2:gpr32 = ADDWrr %0, %1
    B %bb.3

  bb.2:
    successors: %bb.3
    %3:gpr32 = MADDWrrr %0, %1, $wzr
    B %bb.3

  bb.3:
    %4:gpr32 = PHI %2, %bb.1, %3, %bb.2
    %5:gpr32 = ADDWrr killed %4, %0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...