; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=arm64-apple-ios7.0 -stop-after=finalize-isel -o - %s | FileCheck %s

define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x4(ptr %A, ptr %ptr) {
  ; CHECK-LABEL: name: test_v16i8_post_imm_ld1x4
  ; CHECK: bb.0 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $x0, $x1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY $x1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
  ; CHECK-NEXT:   [[LD1Fourv16b_POST:%[0-9]+]]:gpr64common, [[LD1Fourv16b_POST1:%[0-9]+]]:qqqq = LD1Fourv16b_POST [[COPY1]], $xzr :: (load (s512) from %ir.A)
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr128 = COPY [[LD1Fourv16b_POST1]].qsub0
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr128 = COPY [[LD1Fourv16b_POST1]].qsub1
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:fpr128 = COPY [[LD1Fourv16b_POST1]].qsub2
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:fpr128 = COPY [[LD1Fourv16b_POST1]].qsub3
  ; CHECK-NEXT:   STRXui killed [[LD1Fourv16b_POST]], [[COPY]], 0 :: (store (s64) into %ir.ptr)
  ; CHECK-NEXT:   $q0 = COPY [[COPY2]]
  ; CHECK-NEXT:   $q1 = COPY [[COPY3]]
  ; CHECK-NEXT:   $q2 = COPY [[COPY4]]
  ; CHECK-NEXT:   $q3 = COPY [[COPY5]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
  %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr %A)
  %tmp = getelementptr i8, ptr %A, i32 64
  store ptr %tmp, ptr %ptr
  ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4
}

define ptr @test_v1i64_post_imm_st2(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C) nounwind {
  ; CHECK-LABEL: name: test_v1i64_post_imm_st2
  ; CHECK: bb.0 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $x0, $d0, $d1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr64 = COPY $d1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
  ; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE [[COPY1]], %subreg.dsub0, [[COPY]], %subreg.dsub1
  ; CHECK-NEXT:   [[ST1Twov1d_POST:%[0-9]+]]:gpr64sp = ST1Twov1d_POST killed [[REG_SEQUENCE]], [[COPY2]], $xzr :: (store (s128) into %ir.A)
  ; CHECK-NEXT:   $x0 = COPY [[ST1Twov1d_POST]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
  call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> %B, <1 x i64> %C, ptr %A)
  %tmp = getelementptr i64, ptr %A, i64 2
  ret ptr %tmp
}