; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define i64 @testmsxs(float %x) {
; CHECK-LABEL: testmsxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtas w8, s0
; CHECK-NEXT:    sxtw x0, w8
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lround.i32.f32(float %x)
  %conv = sext i32 %0 to i64
  ret i64 %conv
}

define i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtas w0, s0
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lround.i32.f32(float %x)
  ret i32 %0
}

define i64 @testmsxd(double %x) {
; CHECK-LABEL: testmsxd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtas w8, d0
; CHECK-NEXT:    sxtw x0, w8
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lround.i32.f64(double %x)
  %conv = sext i32 %0 to i64
  ret i64 %conv
}

define i32 @testmswd(double %x) {
; CHECK-LABEL: testmswd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtas w0, d0
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lround.i32.f64(double %x)
  ret i32 %0
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}