# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+sme -run-pass=aarch64-machine-sme-abi -verify-machineinstrs %s -o - | FileCheck %s --- | ; Tests we skip debug instructions when computing liveness. define void @skip_debug_instructions() "aarch64_inout_za" { ret void } declare void @clobber() !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3} !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, imports: !2, splitDebugInlining: false, nameTableKind: None) !1 = !DIFile(filename: "test.cpp", directory: "dir", checksumkind: CSK_MD5, checksum: "6cd3cbff285d245f25d9b3f1d7552e31") !2 = !{} !3 = !{i32 2, !"Debug Info Version", i32 3} !4 = !DILocalVariable(name: "this", arg: 1, scope: !5, type: !15, flags: DIFlagArtificial | DIFlagObjectPointer) !5 = distinct !DISubprogram(name: "operator()", linkageName: "test", scope: !7, file: !6, line: 347, type: !13, scopeLine: 347, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !0, declaration: !14, retainedNodes: !2, keyInstructions: true) !6 = !DIFile(filename: "test.cpp", directory: "dir", checksumkind: CSK_MD5, checksum: "6cd3cbff285d245f25d9b3f1d7552e31") !7 = distinct !DICompositeType(tag: DW_TAG_class_type, scope: !8, file: !6, line: 347, size: 896, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !2) !8 = distinct !DISubprogram(name: "test", linkageName: "test", scope: !9, file: !6, line: 327, type: !11, scopeLine: 336, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2, keyInstructions: true) !9 = !DINamespace(name: "test", scope: !10) !10 = !DINamespace(name: "test", scope: null) !11 = distinct !DISubroutineType(types: !12) !12 = !{null} !13 = distinct !DISubroutineType(types: !12) !14 = !DISubprogram(name: "operator()", scope: !7, file: !6, line: 347, type: !13, scopeLine: 347, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagOptimized) !15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64) !16 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !7) !17 = !DILocation(line: 0, scope: !5) ... --- name: skip_debug_instructions tracksRegLiveness: true isSSA: true noVRegs: false body: | bb.0: ; CHECK-LABEL: name: skip_debug_instructions ; CHECK: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $sp ; CHECK-NEXT: [[MSUBXrrr:%[0-9]+]]:gpr64 = MSUBXrrr [[RDSVLI_XI]], [[RDSVLI_XI]], [[COPY]] ; CHECK-NEXT: $sp = COPY [[MSUBXrrr]] ; CHECK-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]] ; CHECK-NEXT: MSR 56965, [[COPY1]] ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp ; CHECK-NEXT: RequiresZASavePseudo ; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp ; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv ; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0 ; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0 ; CHECK-NEXT: MSR 56965, $xzr ; CHECK-NEXT: $nzcv = IMPLICIT_DEF ; CHECK-NEXT: DBG_VALUE $w0, $noreg ; CHECK-NEXT: $zab0 = IMPLICIT_DEF ; CHECK-NEXT: FAKE_USE $nzcv ; CHECK-NEXT: RET_ReallyLR ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp RequiresZASavePseudo BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp $nzcv = IMPLICIT_DEF DBG_VALUE $w0, $noreg, !4, !DIExpression(), debug-location !17 $zab0 = IMPLICIT_DEF FAKE_USE $nzcv RET_ReallyLR ...