; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple aarch64 -mattr=+sve < %s | FileCheck %s

define <vscale x 4 x i16> @sdiv_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m) {
; CHECK-LABEL: sdiv_nxv4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.s
; CHECK-NEXT:    sxth z1.s, p1/m, z1.s
; CHECK-NEXT:    sxth z0.s, p1/m, z0.s
; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i16> @llvm.masked.sdiv(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
  ret <vscale x 4 x i16> %res
}

define <vscale x 4 x i32> @sdiv_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m) {
; CHECK-LABEL: sdiv_nxv4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i32> @llvm.masked.sdiv(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
  ret <vscale x 4 x i32> %res
}

define <vscale x 8 x i32> @sdiv_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: sdiv_nxv8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpklo p1.h, p0.b
; CHECK-NEXT:    punpkhi p0.h, p0.b
; CHECK-NEXT:    sdiv z0.s, p1/m, z0.s, z2.s
; CHECK-NEXT:    sdiv z1.s, p0/m, z1.s, z3.s
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i32> @llvm.masked.sdiv(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i32> %res
}

define <vscale x 8 x i16> @sdiv_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: sdiv_nxv8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z2.h, #1 // =0x1
; CHECK-NEXT:    sel z1.h, p0, z1.h, z2.h
; CHECK-NEXT:    sunpkhi z2.s, z0.h
; CHECK-NEXT:    sunpklo z0.s, z0.h
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    sunpkhi z3.s, z1.h
; CHECK-NEXT:    sunpklo z1.s, z1.h
; CHECK-NEXT:    sdiv z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.masked.sdiv(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i16> %res
}

define <vscale x 2 x i64> @sdiv_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: sdiv_nxv2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sdiv z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i64> @llvm.masked.sdiv(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
  ret <vscale x 2 x i64> %res
}