; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple aarch64-none-linux-gnu -stop-after=finalize-isel | FileCheck %s --check-prefix=CHECK

define half @test_vext_v8i16_0(<8 x i16> %a) {
  ; CHECK-LABEL: name: test_vext_v8i16_0
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $q0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr128 = COPY $q0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
  ; CHECK-NEXT:   $h0 = COPY [[COPY1]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $h0
entry:
  %b = extractelement <8 x i16> %a, i32 0
  %c = bitcast i16 %b to half
  ret half %c
}