; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s

;; This used to crash mid-legalization because we'd no longer have BUILD_VECTOR,
;; but an CONCAT_VECTOR, and we didn't anticipate that.

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

define linkonce_odr void @_ZN1y2beEPiRK1vPmPS1_(<8 x i8> %0, ptr %agg.tmp.i) {
; CHECK-LABEL: _ZN1y2beEPiRK1vPmPS1_:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    mov b1, v0.b[7]
; CHECK-NEXT:    mov b2, v0.b[6]
; CHECK-NEXT:    stur b0, [sp, #15]
; CHECK-NEXT:    stur b0, [sp, #14]
; CHECK-NEXT:    stur b0, [sp, #13]
; CHECK-NEXT:    stur b0, [sp, #12]
; CHECK-NEXT:    stur b1, [sp, #7]
; CHECK-NEXT:    mov b1, v0.b[5]
; CHECK-NEXT:    stur b2, [sp, #6]
; CHECK-NEXT:    mov b2, v0.b[4]
; CHECK-NEXT:    stur b0, [sp, #11]
; CHECK-NEXT:    stur b0, [sp, #10]
; CHECK-NEXT:    stur b1, [sp, #5]
; CHECK-NEXT:    mov b1, v0.b[3]
; CHECK-NEXT:    stur b0, [sp, #9]
; CHECK-NEXT:    stur b2, [sp, #4]
; CHECK-NEXT:    mov b2, v0.b[2]
; CHECK-NEXT:    str b0, [sp]
; CHECK-NEXT:    mov b0, v0.b[1]
; CHECK-NEXT:    stur b1, [sp, #3]
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    stur b2, [sp, #2]
; CHECK-NEXT:    stur b0, [sp, #8]
; CHECK-NEXT:    stur b0, [sp, #1]
; CHECK-NEXT:    ldr q0, [sp]
; CHECK-NEXT:    stp q0, q1, [x0]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
entry:
  %ref.tmp6.sroa.0.0.vecblend.i = shufflevector <8 x i8> %0, <8 x i8> zeroinitializer, <24 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %ref.tmp6.sroa.0.20.vecblend.i = shufflevector <24 x i8> %ref.tmp6.sroa.0.0.vecblend.i, <24 x i8> zeroinitializer, <24 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 45, i32 46, i32 47>
  %ref.tmp.sroa.0.0.vecblend.i = shufflevector <24 x i8> %ref.tmp6.sroa.0.20.vecblend.i, <24 x i8> zeroinitializer, <28 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef>
  %n.sroa.0.0.vecblend.i.i = shufflevector <28 x i8> %ref.tmp.sroa.0.0.vecblend.i, <28 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 undef, i32 undef, i32 undef, i32 undef>
  store <32 x i8> %n.sroa.0.0.vecblend.i.i, ptr %agg.tmp.i, align 4
  ret void
}