; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple aarch64 -global-isel -global-isel-abort=2 -mattr=+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI-FP16

; CHECK-GI-FP16:       warning: Instruction selection used fallback path for testmuwbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testmuxbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testpuwbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testpuxbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testzuwbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testzuxbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testauwbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testauxbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testnuwbf
; CHECK-GI-FP16-NEXT:  warning: Instruction selection used fallback path for testnuxbf

; Round towards minus infinity (fcvtmu).

define i32 @testmuwbf(bfloat %a) {
; CHECK-LABEL: testmuwbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintm s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.floor.bf16(bfloat %a)
  %i = call i32 @llvm.fptoui.sat.i32.bf16(bfloat %r)
  ret i32 %i
}

define i64 @testmuxbf(bfloat %a) {
; CHECK-LABEL: testmuxbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintm s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.floor.bf16(bfloat %a)
  %i = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %r)
  ret i64 %i
}

define i32 @testmuwh(half %a) {
; CHECK-CVT-LABEL: testmuwh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintm s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu w0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testmuwh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtmu w0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testmuwh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintm s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu w0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testmuwh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtmu w0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.floor.f16(half %a)
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  ret i32 %i
}

define i64 @testmuxh(half %a) {
; CHECK-CVT-LABEL: testmuxh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintm s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu x0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testmuxh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtmu x0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testmuxh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintm s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu x0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testmuxh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtmu x0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.floor.f16(half %a)
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  ret i64 %i
}

define i32 @testmuws(float %a) {
; CHECK-LABEL: testmuws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtmu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.floor.f32(float %a)
  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
  ret i32 %i
}

define i64 @testmuxs(float %a) {
; CHECK-LABEL: testmuxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtmu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.floor.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  ret i64 %i
}

define i32 @testmuwd(double %a) {
; CHECK-LABEL: testmuwd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtmu w0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.floor.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  ret i32 %i
}

define i64 @testmuxd(double %a) {
; CHECK-LABEL: testmuxd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtmu x0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.floor.f64(double %a)
  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
  ret i64 %i
}

; Round towards plus infinity (fcvtpu).

define i32 @testpuwbf(bfloat %a) {
; CHECK-LABEL: testpuwbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintp s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.ceil.bf16(bfloat %a)
  %i = call i32 @llvm.fptoui.sat.i32.bf16(bfloat %r)
  ret i32 %i
}

define i64 @testpuxbf(bfloat %a) {
; CHECK-LABEL: testpuxbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintp s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.ceil.bf16(bfloat %a)
  %i = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %r)
  ret i64 %i
}

define i32 @testpuwh(half %a) {
; CHECK-CVT-LABEL: testpuwh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintp s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu w0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testpuwh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtpu w0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testpuwh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintp s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu w0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testpuwh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtpu w0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.ceil.f16(half %a)
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  ret i32 %i
}

define i64 @testpuxh(half %a) {
; CHECK-CVT-LABEL: testpuxh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintp s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu x0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testpuxh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtpu x0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testpuxh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintp s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu x0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testpuxh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtpu x0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.ceil.f16(half %a)
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  ret i64 %i
}

define i32 @testpuws(float %a) {
; CHECK-LABEL: testpuws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtpu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.ceil.f32(float %a)
  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
  ret i32 %i
}

define i64 @testpuxs(float %a) {
; CHECK-LABEL: testpuxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtpu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.ceil.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  ret i64 %i
}

define i32 @testpuwd(double %a) {
; CHECK-LABEL: testpuwd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtpu w0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.ceil.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  ret i32 %i
}

define i64 @testpuxd(double %a) {
; CHECK-LABEL: testpuxd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtpu x0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.ceil.f64(double %a)
  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
  ret i64 %i
}

; Round towards zero (fcvtzu).

define i32 @testzuwbf(bfloat %a) {
; CHECK-LABEL: testzuwbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintz s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.trunc.bf16(bfloat %a)
  %i = call i32 @llvm.fptoui.sat.i32.bf16(bfloat %r)
  ret i32 %i
}

define i64 @testzuxbf(bfloat %a) {
; CHECK-LABEL: testzuxbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintz s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.trunc.bf16(bfloat %a)
  %i = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %r)
  ret i64 %i
}

define i32 @testzuwh(half %a) {
; CHECK-CVT-LABEL: testzuwh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintz s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu w0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testzuwh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtzu w0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testzuwh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintz s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu w0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testzuwh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtzu w0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.trunc.f16(half %a)
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  ret i32 %i
}

define i64 @testzuxh(half %a) {
; CHECK-CVT-LABEL: testzuxh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintz s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu x0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testzuxh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtzu x0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testzuxh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintz s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu x0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testzuxh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtzu x0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.trunc.f16(half %a)
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  ret i64 %i
}

define i32 @testzuws(float %a) {
; CHECK-LABEL: testzuws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.trunc.f32(float %a)
  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
  ret i32 %i
}

define i64 @testzuxs(float %a) {
; CHECK-LABEL: testzuxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.trunc.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  ret i64 %i
}

define i32 @testzuwd(double %a) {
; CHECK-LABEL: testzuwd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzu w0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.trunc.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  ret i32 %i
}

define i64 @testzuxd(double %a) {
; CHECK-LABEL: testzuxd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzu x0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.trunc.f64(double %a)
  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
  ret i64 %i
}

; Round to nearest, ties away from zero (fcvtau).

define i32 @testauwbf(bfloat %a) {
; CHECK-LABEL: testauwbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frinta s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.round.bf16(bfloat %a)
  %i = call i32 @llvm.fptoui.sat.i32.bf16(bfloat %r)
  ret i32 %i
}

define i64 @testauxbf(bfloat %a) {
; CHECK-LABEL: testauxbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frinta s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.round.bf16(bfloat %a)
  %i = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %r)
  ret i64 %i
}

define i32 @testauwh(half %a) {
; CHECK-CVT-LABEL: testauwh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frinta s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu w0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testauwh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtau w0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testauwh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frinta s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu w0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testauwh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtau w0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.round.f16(half %a)
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  ret i32 %i
}

define i64 @testauxh(half %a) {
; CHECK-CVT-LABEL: testauxh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frinta s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu x0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testauxh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtau x0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testauxh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frinta s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu x0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testauxh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtau x0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.round.f16(half %a)
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  ret i64 %i
}

define i32 @testauws(float %a) {
; CHECK-LABEL: testauws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtau w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.round.f32(float %a)
  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
  ret i32 %i
}

define i64 @testauxs(float %a) {
; CHECK-LABEL: testauxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtau x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.round.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  ret i64 %i
}

define i32 @testauwd(double %a) {
; CHECK-LABEL: testauwd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtau w0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.round.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  ret i32 %i
}

define i64 @testauxd(double %a) {
; CHECK-LABEL: testauxd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtau x0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.round.f64(double %a)
  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
  ret i64 %i
}

; Round to nearest, ties to even (fcvtnu).

define i32 @testnuwbf(bfloat %a) {
; CHECK-LABEL: testnuwbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintn s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.roundeven.bf16(bfloat %a)
  %i = call i32 @llvm.fptoui.sat.i32.bf16(bfloat %r)
  ret i32 %i
}

define i64 @testnuxbf(bfloat %a) {
; CHECK-LABEL: testnuxbf:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    mov w8, #32767 // =0x7fff
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    frintn s0, s0
; CHECK-NEXT:    fmov w9, s0
; CHECK-NEXT:    ubfx w10, w9, #16, #1
; CHECK-NEXT:    add w8, w9, w8
; CHECK-NEXT:    add w8, w10, w8
; CHECK-NEXT:    lsr w8, w8, #16
; CHECK-NEXT:    fmov s0, w8
; CHECK-NEXT:    shll v0.4s, v0.4h, #16
; CHECK-NEXT:    fcvtzu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call bfloat @llvm.roundeven.bf16(bfloat %a)
  %i = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %r)
  ret i64 %i
}

define i32 @testnuwh(half %a) {
; CHECK-CVT-LABEL: testnuwh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintn s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu w0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testnuwh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtnu w0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testnuwh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintn s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu w0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testnuwh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtnu w0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.roundeven.f16(half %a)
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  ret i32 %i
}

define i64 @testnuxh(half %a) {
; CHECK-CVT-LABEL: testnuxh:
; CHECK-CVT:       // %bb.0: // %entry
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    frintn s0, s0
; CHECK-CVT-NEXT:    fcvt h0, s0
; CHECK-CVT-NEXT:    fcvt s0, h0
; CHECK-CVT-NEXT:    fcvtzu x0, s0
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: testnuxh:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fcvtnu x0, h0
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-LABEL: testnuxh:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    frintn s0, s0
; CHECK-GI-NEXT:    fcvt h0, s0
; CHECK-GI-NEXT:    fcvt s0, h0
; CHECK-GI-NEXT:    fcvtzu x0, s0
; CHECK-GI-NEXT:    ret
;
; CHECK-GI-FP16-LABEL: testnuxh:
; CHECK-GI-FP16:       // %bb.0: // %entry
; CHECK-GI-FP16-NEXT:    fcvtnu x0, h0
; CHECK-GI-FP16-NEXT:    ret
entry:
  %r = call half @llvm.roundeven.f16(half %a)
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  ret i64 %i
}

define i32 @testnuws(float %a) {
; CHECK-LABEL: testnuws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtnu w0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.roundeven.f32(float %a)
  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
  ret i32 %i
}

define i64 @testnuxs(float %a) {
; CHECK-LABEL: testnuxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtnu x0, s0
; CHECK-NEXT:    ret
entry:
  %r = call float @llvm.roundeven.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  ret i64 %i
}

define i32 @testnuwd(double %a) {
; CHECK-LABEL: testnuwd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtnu w0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.roundeven.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  ret i32 %i
}

define i64 @testnuxd(double %a) {
; CHECK-LABEL: testnuxd:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtnu x0, d0
; CHECK-NEXT:    ret
entry:
  %r = call double @llvm.roundeven.f64(double %a)
  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
  ret i64 %i
}