; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -verify-machineinstrs -force-streaming < %s | FileCheck %s target triple = "aarch64-linux" define {, , , } @test_luti4_zt_i8( %v0, %v1) #0 { ; CHECK-LABEL: test_luti4_zt_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: luti4 { z0.b - z3.b }, zt0, { z0, z1 } ; CHECK-NEXT: ret %res = call {, , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %v0, %v1) ret {, , , } %res } ; Tests multiple identical luti4 intrinsics with ZT0 loads interspersed, are not CSD'd. define void @test_multiple_luti4_zt_i8(ptr %ptrA, ptr %ptrB, %v0, %v1) #0 { ; CHECK-LABEL: test_multiple_luti4_zt_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr zt0, [x0] ; CHECK-NEXT: luti4 { z4.b - z7.b }, zt0, { z0, z1 } ; CHECK-NEXT: // fake_use: $z4 ; CHECK-NEXT: ldr zt0, [x1] ; CHECK-NEXT: luti4 { z0.b - z3.b }, zt0, { z0, z1 } ; CHECK-NEXT: // fake_use: $z0 ; CHECK-NEXT: ret tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr %ptrA) %res1 = call {, , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %v0, %v1) tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr %ptrB) %res2 = call {, , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %v0, %v1) call void (...) @llvm.fake.use({ , , , } %res1) call void (...) @llvm.fake.use({ , , , } %res2) ret void } attributes #0 = { "target-features"="+sme2,+sme-lutv2"}