; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve,+bf16             < %s | FileCheck %s --check-prefixes=SVE
; RUN: llc -mattr=+sve,+bf16,+sve-b16b16 < %s | FileCheck %s --check-prefixes=SVE-B16B16

target triple = "aarch64-unknown-linux-gnu"

define <vscale x 8 x bfloat> @fmla_nxv8bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
; SVE-LABEL: fmla_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    uunpkhi z4.s, z2.h
; SVE-NEXT:    uunpkhi z5.s, z1.h
; SVE-NEXT:    uunpklo z2.s, z2.h
; SVE-NEXT:    uunpklo z1.s, z1.h
; SVE-NEXT:    ptrue p0.s
; SVE-NEXT:    zip2 z6.h, z3.h, z0.h
; SVE-NEXT:    zip1 z0.h, z3.h, z0.h
; SVE-NEXT:    bfmlalb z6.s, z5.h, z4.h
; SVE-NEXT:    bfmlalb z0.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z1.h, p0/m, z6.s
; SVE-NEXT:    bfcvt z0.h, p0/m, z0.s
; SVE-NEXT:    uzp1 z0.h, z0.h, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmla_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    ptrue p0.h
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
  %res = fadd contract <vscale x 8 x bfloat> %acc, %mul
  ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x bfloat> @fmla_nxv4bf16(<vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
; SVE-LABEL: fmla_nxv4bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    lsl z0.s, z0.s, #16
; SVE-NEXT:    ptrue p0.s
; SVE-NEXT:    bfmlalb z0.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z0.h, p0/m, z0.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmla_nxv4bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    ptrue p0.s
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
  %res = fadd contract <vscale x 4 x bfloat> %acc, %mul
  ret <vscale x 4 x bfloat> %res
}

define <vscale x 2 x bfloat> @fmla_nxv2bf16(<vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
; SVE-LABEL: fmla_nxv2bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    lsl z2.s, z2.s, #16
; SVE-NEXT:    lsl z1.s, z1.s, #16
; SVE-NEXT:    lsl z0.s, z0.s, #16
; SVE-NEXT:    ptrue p0.d
; SVE-NEXT:    fmla z0.s, p0/m, z1.s, z2.s
; SVE-NEXT:    bfcvt z0.h, p0/m, z0.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmla_nxv2bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    ptrue p0.d
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
  %res = fadd contract <vscale x 2 x bfloat> %acc, %mul
  ret <vscale x 2 x bfloat> %res
}

define <vscale x 8 x bfloat> @fmls_nxv8bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
; SVE-LABEL: fmls_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    ptrue p0.h
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    uunpkhi z5.s, z2.h
; SVE-NEXT:    uunpklo z2.s, z2.h
; SVE-NEXT:    fneg z1.h, p0/m, z1.h
; SVE-NEXT:    ptrue p0.s
; SVE-NEXT:    zip2 z6.h, z3.h, z0.h
; SVE-NEXT:    zip1 z0.h, z3.h, z0.h
; SVE-NEXT:    uunpkhi z4.s, z1.h
; SVE-NEXT:    uunpklo z1.s, z1.h
; SVE-NEXT:    bfmlalb z6.s, z4.h, z5.h
; SVE-NEXT:    bfmlalb z0.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z1.h, p0/m, z6.s
; SVE-NEXT:    bfcvt z0.h, p0/m, z0.s
; SVE-NEXT:    uzp1 z0.h, z0.h, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmls_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    ptrue p0.h
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
  %res = fsub contract <vscale x 8 x bfloat> %acc, %mul
  ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x bfloat> @fmls_nxv4bf16(<vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
; SVE-LABEL: fmls_nxv4bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    ptrue p0.s
; SVE-NEXT:    lsl z0.s, z0.s, #16
; SVE-NEXT:    fneg z1.h, p0/m, z1.h
; SVE-NEXT:    bfmlalb z0.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z0.h, p0/m, z0.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmls_nxv4bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    ptrue p0.s
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
  %res = fsub contract <vscale x 4 x bfloat> %acc, %mul
  ret <vscale x 4 x bfloat> %res
}

define <vscale x 2 x bfloat> @fmls_nxv2bf16(<vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
; SVE-LABEL: fmls_nxv2bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    ptrue p0.d
; SVE-NEXT:    lsl z2.s, z2.s, #16
; SVE-NEXT:    lsl z0.s, z0.s, #16
; SVE-NEXT:    fneg z1.h, p0/m, z1.h
; SVE-NEXT:    lsl z1.s, z1.s, #16
; SVE-NEXT:    fmla z0.s, p0/m, z1.s, z2.s
; SVE-NEXT:    bfcvt z0.h, p0/m, z0.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmls_nxv2bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    ptrue p0.d
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
  %res = fsub contract <vscale x 2 x bfloat> %acc, %mul
  ret <vscale x 2 x bfloat> %res
}

define <vscale x 8 x bfloat> @fmla_sel_nxv8bf16(<vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
; SVE-LABEL: fmla_sel_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    uunpkhi z4.s, z2.h
; SVE-NEXT:    uunpkhi z5.s, z1.h
; SVE-NEXT:    uunpklo z2.s, z2.h
; SVE-NEXT:    uunpklo z1.s, z1.h
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    zip2 z6.h, z3.h, z0.h
; SVE-NEXT:    zip1 z3.h, z3.h, z0.h
; SVE-NEXT:    bfmlalb z6.s, z5.h, z4.h
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z1.h, p1/m, z6.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    uzp1 z1.h, z2.h, z1.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmla_sel_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
  %add = fadd contract <vscale x 8 x bfloat> %acc, %mul
  %res = select <vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %add, <vscale x 8 x bfloat> %acc
  ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x bfloat> @fmla_sel_nxv4bf16(<vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
; SVE-LABEL: fmla_sel_nxv4bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    lsl z3.s, z0.s, #16
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z0.h, p0/m, z3.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmla_sel_nxv4bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
  %add = fadd contract <vscale x 4 x bfloat> %acc, %mul
  %res = select <vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %add, <vscale x 4 x bfloat> %acc
  ret <vscale x 4 x bfloat> %res
}

define <vscale x 2 x bfloat> @fmla_sel_nxv2bf16(<vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
; SVE-LABEL: fmla_sel_nxv2bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    lsl z2.s, z2.s, #16
; SVE-NEXT:    lsl z1.s, z1.s, #16
; SVE-NEXT:    lsl z3.s, z0.s, #16
; SVE-NEXT:    ptrue p1.d
; SVE-NEXT:    fmad z1.s, p1/m, z2.s, z3.s
; SVE-NEXT:    bfcvt z0.h, p0/m, z1.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmla_sel_nxv2bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
  %add = fadd contract <vscale x 2 x bfloat> %acc, %mul
  %res = select <vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %add, <vscale x 2 x bfloat> %acc
  ret <vscale x 2 x bfloat> %res
}

define <vscale x 8 x bfloat> @fmls_sel_nxv8bf16(<vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
; SVE-LABEL: fmls_sel_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    ptrue p1.h
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    uunpkhi z5.s, z2.h
; SVE-NEXT:    uunpklo z2.s, z2.h
; SVE-NEXT:    fneg z1.h, p1/m, z1.h
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    zip2 z6.h, z3.h, z0.h
; SVE-NEXT:    zip1 z3.h, z3.h, z0.h
; SVE-NEXT:    uunpkhi z4.s, z1.h
; SVE-NEXT:    uunpklo z1.s, z1.h
; SVE-NEXT:    bfmlalb z6.s, z4.h, z5.h
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z1.h, p1/m, z6.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    uzp1 z1.h, z2.h, z1.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmls_sel_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
  %sub = fsub contract <vscale x 8 x bfloat> %acc, %mul
  %res = select <vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %sub, <vscale x 8 x bfloat> %acc
  ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x bfloat> @fmls_sel_nxv4bf16(<vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
; SVE-LABEL: fmls_sel_nxv4bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    lsl z3.s, z0.s, #16
; SVE-NEXT:    fneg z1.h, p1/m, z1.h
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfcvt z0.h, p0/m, z3.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmls_sel_nxv4bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
  %sub = fsub contract <vscale x 4 x bfloat> %acc, %mul
  %res = select <vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %sub, <vscale x 4 x bfloat> %acc
  ret <vscale x 4 x bfloat> %res
}

define <vscale x 2 x bfloat> @fmls_sel_nxv2bf16(<vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
; SVE-LABEL: fmls_sel_nxv2bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    ptrue p1.d
; SVE-NEXT:    lsl z2.s, z2.s, #16
; SVE-NEXT:    lsl z3.s, z0.s, #16
; SVE-NEXT:    fneg z1.h, p1/m, z1.h
; SVE-NEXT:    lsl z1.s, z1.s, #16
; SVE-NEXT:    fmad z1.s, p1/m, z2.s, z3.s
; SVE-NEXT:    bfcvt z0.h, p0/m, z1.s
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fmls_sel_nxv2bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
  %sub = fsub contract <vscale x 2 x bfloat> %acc, %mul
  %res = select <vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %sub, <vscale x 2 x bfloat> %acc
  ret <vscale x 2 x bfloat> %res
}

define <vscale x 8 x bfloat> @fadd_sel_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fadd z3.s, z4.s, z3.s
; SVE-NEXT:    fadd z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fadd_sel_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfadd z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT:    ret
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> zeroinitializer
  %fadd = fadd nsz <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fadd
}

define <vscale x 8 x bfloat> @fsub_sel_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fsub z3.s, z4.s, z3.s
; SVE-NEXT:    fsub z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fsub_sel_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfsub z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT:    ret
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> zeroinitializer
  %fsub = fsub <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fsub
}

define <vscale x 8 x bfloat> @fadd_sel_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_negzero_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fadd z3.s, z4.s, z3.s
; SVE-NEXT:    fadd z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fadd_sel_negzero_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfadd z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT:    ret
  %nz = fneg <vscale x 8 x bfloat> zeroinitializer
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %nz
  %fadd = fadd <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fadd
}

define <vscale x 8 x bfloat> @fsub_sel_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_negzero_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fsub z3.s, z4.s, z3.s
; SVE-NEXT:    fsub z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fsub_sel_negzero_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfsub z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT:    ret
  %nz = fneg <vscale x 8 x bfloat> zeroinitializer
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %nz
  %fsub = fsub nsz <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fsub
}

define <vscale x 8 x bfloat> @fadd_sel_fmul_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_fmul_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z3.s, #0x80000000
; SVE-NEXT:    mov z4.s, #0x80000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip1 z0.h, z2.h, z0.h
; SVE-NEXT:    sel z1.h, p0, z1.h, z2.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    fadd z2.s, z4.s, z3.s
; SVE-NEXT:    fadd z0.s, z0.s, z1.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z2.s
; SVE-NEXT:    bfcvt z0.h, p1/m, z0.s
; SVE-NEXT:    uzp1 z0.h, z0.h, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fadd_sel_fmul_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    movi v3.2d, #0000000000000000
; SVE-B16B16-NEXT:    bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT:    sel z1.h, p0, z1.h, z3.h
; SVE-B16B16-NEXT:    bfadd z0.h, z0.h, z1.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
  %fadd = fadd contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fadd
}

define <vscale x 8 x bfloat> @fsub_sel_fmul_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_fmul_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z3.s, #0x80000000
; SVE-NEXT:    mov z4.s, #0x80000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fsub z3.s, z4.s, z3.s
; SVE-NEXT:    fsub z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fsub_sel_fmul_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
  %fsub = fsub contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fsub
}

define <vscale x 8 x bfloat> @fadd_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_fmul_nsz_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    movi v4.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fadd z3.s, z4.s, z3.s
; SVE-NEXT:    fadd z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fadd_sel_fmul_nsz_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
  %fadd = fadd nsz contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fadd
}

define <vscale x 8 x bfloat> @fsub_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_fmul_nsz_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    movi v4.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fsub z3.s, z4.s, z3.s
; SVE-NEXT:    fsub z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fsub_sel_fmul_nsz_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
  %fsub = fsub nsz contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fsub
}

define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_fmul_negzero_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z3.s, #0x80000000
; SVE-NEXT:    mov z4.s, #0x80000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fadd z3.s, z4.s, z3.s
; SVE-NEXT:    fadd z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fadd_sel_fmul_negzero_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %nz = fneg <vscale x 8 x bfloat> zeroinitializer
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
  %fadd = fadd contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fadd
}

define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_fmul_negzero_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z3.s, #0x80000000
; SVE-NEXT:    mov z4.s, #0x80000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    dupm z2.h, #0x8000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z3.h, z0.h
; SVE-NEXT:    zip1 z0.h, z3.h, z0.h
; SVE-NEXT:    sel z1.h, p0, z1.h, z2.h
; SVE-NEXT:    zip2 z2.h, z3.h, z1.h
; SVE-NEXT:    zip1 z1.h, z3.h, z1.h
; SVE-NEXT:    fsub z2.s, z4.s, z2.s
; SVE-NEXT:    fsub z0.s, z0.s, z1.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z2.s
; SVE-NEXT:    bfcvt z0.h, p1/m, z0.s
; SVE-NEXT:    uzp1 z0.h, z0.h, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fsub_sel_fmul_negzero_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    dupm z3.h, #0x8000
; SVE-B16B16-NEXT:    bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT:    sel z1.h, p0, z1.h, z3.h
; SVE-B16B16-NEXT:    bfsub z0.h, z0.h, z1.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %nz = fneg <vscale x 8 x bfloat> zeroinitializer
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
  %fsub = fsub contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fsub
}

define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_fmul_negzero_nsz_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    movi v4.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fadd z3.s, z4.s, z3.s
; SVE-NEXT:    fadd z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fadd_sel_fmul_negzero_nsz_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %nz = fneg <vscale x 8 x bfloat> zeroinitializer
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
  %fadd = fadd nsz contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fadd
}

define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_fmul_negzero_nsz_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    movi v3.2d, #0000000000000000
; SVE-NEXT:    movi v4.2d, #0000000000000000
; SVE-NEXT:    ptrue p1.s
; SVE-NEXT:    bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z4.s, z1.h, z2.h
; SVE-NEXT:    movi v2.2d, #0000000000000000
; SVE-NEXT:    bfcvt z1.h, p1/m, z3.s
; SVE-NEXT:    bfcvtnt z1.h, p1/m, z4.s
; SVE-NEXT:    zip2 z4.h, z2.h, z0.h
; SVE-NEXT:    zip2 z3.h, z2.h, z1.h
; SVE-NEXT:    zip1 z1.h, z2.h, z1.h
; SVE-NEXT:    zip1 z2.h, z2.h, z0.h
; SVE-NEXT:    fsub z3.s, z4.s, z3.s
; SVE-NEXT:    fsub z1.s, z2.s, z1.s
; SVE-NEXT:    bfcvt z2.h, p1/m, z3.s
; SVE-NEXT:    bfcvt z1.h, p1/m, z1.s
; SVE-NEXT:    uzp1 z1.h, z1.h, z2.h
; SVE-NEXT:    mov z0.h, p0/m, z1.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: fsub_sel_fmul_negzero_nsz_nxv8bf16:
; SVE-B16B16:       // %bb.0:
; SVE-B16B16-NEXT:    bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
  %fmul = fmul <vscale x 8 x bfloat> %b, %c
  %nz = fneg <vscale x 8 x bfloat> zeroinitializer
  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
  %fsub = fsub nsz contract <vscale x 8 x bfloat> %a, %sel
  ret <vscale x 8 x bfloat> %fsub
}

define <vscale x 4 x float> @partial_reduce_to_nxv4f32(<vscale x 4 x float> %acc, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; SVE-LABEL: partial_reduce_to_nxv4f32:
; SVE:       // %bb.0: // %entry
; SVE-NEXT:    bfmlalb z0.s, z1.h, z2.h
; SVE-NEXT:    bfmlalt z0.s, z1.h, z2.h
; SVE-NEXT:    ret
;
; SVE-B16B16-LABEL: partial_reduce_to_nxv4f32:
; SVE-B16B16:       // %bb.0: // %entry
; SVE-B16B16-NEXT:    bfmlalb z0.s, z1.h, z2.h
; SVE-B16B16-NEXT:    bfmlalt z0.s, z1.h, z2.h
; SVE-B16B16-NEXT:    ret
entry:
  %a.wide = fpext <vscale x 8 x bfloat> %a to <vscale x 8 x float>
  %b.wide = fpext <vscale x 8 x bfloat> %b to <vscale x 8 x float>
  %mult = fmul <vscale x 8 x float> %a.wide, %b.wide
  %partial.reduce = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd(<vscale x 4 x float> %acc, <vscale x 8 x float> %mult)
  ret <vscale x 4 x float> %partial.reduce
}

declare <vscale x 8 x bfloat> @llvm.fma.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)