# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -start-before=greedy -stop-after=virtregrewriter -o - %s | FileCheck %s
--- |
  target triple = "aarch64"

  define aarch64_sve_vector_pcs void @regalloc_hint_cmp_dont_introduce_csr_spill() #0 { unreachable }
  define aarch64_sve_vector_pcs void @regalloc_hint_cmp_reuse_p4() #0 { unreachable }

  attributes #0 = { "target-features"="+sve" }
...

# When suggesting a regalloc hint to choose a distinct destination register for %0,
# avoid using a callee-save register as that will require a spill/fill.
---
name:            regalloc_hint_cmp_dont_introduce_csr_spill
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0, $z0, $z1, $p0, $p1, $p2, $p3

    ; CHECK-LABEL: name: regalloc_hint_cmp_dont_introduce_csr_spill
    ; CHECK: liveins: $p0, $p1, $p2, $p3, $x0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $p0 = CMPEQ_PPzZZ_B $p0, $z0, $z1, implicit-def dead $nzcv
    ; CHECK-NEXT: FAKE_USE $p1
    ; CHECK-NEXT: FAKE_USE $p2
    ; CHECK-NEXT: FAKE_USE $p3
    ; CHECK-NEXT: ST1B_IMM $z0, killed renamable $p0, $x0, 0
    ; CHECK-NEXT: RET_ReallyLR
    %0:ppr_3b = CMPEQ_PPzZZ_B $p0, $z0, $z1, implicit-def dead $nzcv
    FAKE_USE $p1
    FAKE_USE $p2
    FAKE_USE $p3
    ST1B_IMM $z0, %0, $x0, 0
    RET_ReallyLR
...

# For this test, the register allocator can safely reuse $p4 because it was already clobbered
# for other purposes.
---
name:            regalloc_hint_cmp_reuse_p4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0, $z0, $z1, $p0, $p1, $p2, $p3

    ; CHECK-LABEL: name: regalloc_hint_cmp_reuse_p4
    ; CHECK: liveins: $p0, $p1, $p2, $p3, $x0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $p4 = IMPLICIT_DEF
    ; CHECK-NEXT: renamable $p4 = CMPEQ_PPzZZ_B $p0, $z0, $z1, implicit-def dead $nzcv
    ; CHECK-NEXT: FAKE_USE $p1
    ; CHECK-NEXT: FAKE_USE $p2
    ; CHECK-NEXT: FAKE_USE $p3
    ; CHECK-NEXT: ST1B_IMM $z0, killed renamable $p4, $x0, 0
    ; CHECK-NEXT: RET_ReallyLR
    $p4 = IMPLICIT_DEF
    %0:ppr_3b = CMPEQ_PPzZZ_B $p0, $z0, $z1, implicit-def dead $nzcv
    FAKE_USE $p1
    FAKE_USE $p2
    FAKE_USE $p3
    ST1B_IMM $z0, %0, $x0, 0
    RET_ReallyLR
...