; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=+sve | FileCheck %s -check-prefixes=CHECK,SVE
; RUN: llc < %s -mattr=+sve,+sme2 | FileCheck %s -check-prefixes=CHECK,SVE
; RUN: llc < %s -mattr=+sme2 -force-streaming | FileCheck %s -check-prefixes=CHECK,SME2,SME2-ALL
; RUN: llc < %s -mattr=+sme2 -force-streaming -aarch64-sve-vector-bits-min=256 | FileCheck %s -check-prefixes=CHECK,SME2,SME2-256

target triple = "aarch64-unknown-linux-gnu"

define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv4f16(<vscale x 4 x half> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z1.s, z0.s, z0.s
; SVE-NEXT:    uzp2 z2.s, z0.s, z0.s
; SVE-NEXT:    uunpklo z0.d, z1.s
; SVE-NEXT:    uunpklo z1.d, z2.s
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.d, z0.s
; SME2-NEXT:    uunpklo z0.d, z0.s
; SME2-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
  ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
}

define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv8f16(<vscale x 8 x half> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z1.h, z0.h, z0.h
; SVE-NEXT:    uzp2 z2.h, z0.h, z0.h
; SVE-NEXT:    uunpklo z0.s, z1.h
; SVE-NEXT:    uunpklo z1.s, z2.h
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.s, z0.h
; SME2-NEXT:    uunpklo z0.s, z0.h
; SME2-NEXT:    uzp { z0.s, z1.s }, z0.s, z1.s
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
  ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
}

define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv16f16(<vscale x 16 x half> %vec) {
; SVE-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.h, z0.h, z1.h
; SVE-NEXT:    uzp2 z1.h, z0.h, z1.h
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.h, z1.h }, z0.h, z1.h
; SME2-NEXT:    ret
  %retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
  ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
}

define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv4f32(<vscale x 4 x float> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z1.s, z0.s, z0.s
; SVE-NEXT:    uzp2 z2.s, z0.s, z0.s
; SVE-NEXT:    uunpklo z0.d, z1.s
; SVE-NEXT:    uunpklo z1.d, z2.s
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.d, z0.s
; SME2-NEXT:    uunpklo z0.d, z0.s
; SME2-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
  ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
}

define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv8f32(<vscale x 8 x float> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.s, z0.s, z1.s
; SVE-NEXT:    uzp2 z1.s, z0.s, z1.s
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.s, z1.s }, z0.s, z1.s
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
  ret {<vscale x 4 x float>, <vscale x 4 x float>} %retval
}

define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv4f64(<vscale x 4 x double> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z1.d, z0.d, z1.d
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
  ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
}

define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv4bf16(<vscale x 4 x bfloat> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z1.s, z0.s, z0.s
; SVE-NEXT:    uzp2 z2.s, z0.s, z0.s
; SVE-NEXT:    uunpklo z0.d, z1.s
; SVE-NEXT:    uunpklo z1.d, z2.s
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.d, z0.s
; SME2-NEXT:    uunpklo z0.d, z0.s
; SME2-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
}

define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv8bf16(<vscale x 8 x bfloat> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z1.h, z0.h, z0.h
; SVE-NEXT:    uzp2 z2.h, z0.h, z0.h
; SVE-NEXT:    uunpklo z0.s, z1.h
; SVE-NEXT:    uunpklo z1.s, z2.h
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.s, z0.h
; SME2-NEXT:    uunpklo z0.s, z0.h
; SME2-NEXT:    uzp { z0.s, z1.s }, z0.s, z1.s
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
}

define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv16bf16(<vscale x 16 x bfloat> %vec) {
; SVE-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.h, z0.h, z1.h
; SVE-NEXT:    uzp2 z1.h, z0.h, z1.h
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.h, z1.h }, z0.h, z1.h
; SME2-NEXT:    ret
  %retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
}

; Integers

define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv32i8(<vscale x 32 x i8> %vec) {
; SVE-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.b, z0.b, z1.b
; SVE-NEXT:    uzp2 z1.b, z0.b, z1.b
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.b, z1.b }, z0.b, z1.b
; SME2-NEXT:    ret
  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
  ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
}

define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv16i16(<vscale x 16 x i16> %vec) {
; SVE-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.h, z0.h, z1.h
; SVE-NEXT:    uzp2 z1.h, z0.h, z1.h
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.h, z1.h }, z0.h, z1.h
; SME2-NEXT:    ret
  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
  ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
}

define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv8i32(<vscale x 8 x i32> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.s, z0.s, z1.s
; SVE-NEXT:    uzp2 z1.s, z0.s, z1.s
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.s, z1.s }, z0.s, z1.s
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
  ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
}

define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv4i64(<vscale x 4 x i64> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z2.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z1.d, z0.d, z1.d
; SVE-NEXT:    mov z0.d, z2.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
  ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
}

define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv6f16(<vscale x 6 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv6f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    uunpkhi z1.s, z0.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpkhi z2.d, z0.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    str z1, [sp, #2, mul vl]
; CHECK-NEXT:    str z2, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave3.nxv6f16(<vscale x 6 x half> %vec)
  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %retval
}

define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv12f16(<vscale x 12 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv12f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpkhi z2.s, z0.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    str z1, [sp, #2, mul vl]
; CHECK-NEXT:    str z2, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave3.nxv12f16(<vscale x 12 x half> %vec)
  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %retval
}

define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv24f16(<vscale x 24 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv24f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave3.nxv24f16(<vscale x 24 x half> %vec)
  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %retval
}

define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv6f32(<vscale x 6 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv6f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpkhi z2.d, z0.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    str z1, [sp, #2, mul vl]
; CHECK-NEXT:    str z2, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave3.nxv6f32(<vscale x 6 x float> %vec)
  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %retval
}

define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv12f32(<vscale x 12 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv12f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave3.nxv12f32(<vscale x 12 x float> %vec)
  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %retval
}

define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv6f64(<vscale x 6 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv6f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave3.nxv6f64(<vscale x 6 x double> %vec)
  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %retval
}

define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv6bf16(<vscale x 6 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv6bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    uunpkhi z1.s, z0.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpkhi z2.d, z0.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    str z1, [sp, #2, mul vl]
; CHECK-NEXT:    str z2, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave3.nxv6bf16(<vscale x 6 x bfloat> %vec)
  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
}

define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv12bf16(<vscale x 12 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv12bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpkhi z2.s, z0.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    str z1, [sp, #2, mul vl]
; CHECK-NEXT:    str z2, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave3.nxv12bf16(<vscale x 12 x bfloat> %vec)
  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
}

define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv24bf16(<vscale x 24 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv24bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave3.nxv24bf16(<vscale x 24 x bfloat> %vec)
  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
}

; Integers

define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv48i8(<vscale x 48 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv48i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3b { z0.b - z2.b }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave3.nxv48i8(<vscale x 48 x i8> %vec)
  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval
}

define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv24i16(<vscale x 24 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv24i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3h { z0.h - z2.h }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave3.nxv24i16(<vscale x 24 x i16> %vec)
  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval
}

define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv12i32(<vscale x 12 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv4i32_nxvv12i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3w { z0.s - z2.s }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave3.nxv12i32(<vscale x 12 x i32> %vec)
  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval
}

define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv6i64(<vscale x 6 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv6i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-3
; CHECK-NEXT:    .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT:    .cfi_offset w29, -16
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    str z2, [sp, #2, mul vl]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ld3d { z0.d - z2.d }, p0/z, [sp]
; CHECK-NEXT:    addvl sp, sp, #3
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave3.nxv6i64(<vscale x 6 x i64> %vec)
  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval
}

define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv64i8(<vscale x 64 x i8> %vec) {
; SVE-LABEL: vector_deinterleave_nxv16i8_nxv64i8:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z4.b, z2.b, z3.b
; SVE-NEXT:    uzp1 z5.b, z0.b, z1.b
; SVE-NEXT:    uzp2 z3.b, z2.b, z3.b
; SVE-NEXT:    uzp2 z6.b, z0.b, z1.b
; SVE-NEXT:    uzp1 z0.b, z5.b, z4.b
; SVE-NEXT:    uzp2 z2.b, z5.b, z4.b
; SVE-NEXT:    uzp1 z1.b, z6.b, z3.b
; SVE-NEXT:    uzp2 z3.b, z6.b, z3.b
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv16i8_nxv64i8:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.b - z3.b }, { z0.b - z3.b }
; SME2-NEXT:    ret
  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave4.nxv64i8(<vscale x 64 x i8> %vec)
  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval
}

define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv32i16(<vscale x 32 x i16> %vec) {
; SVE-LABEL: vector_deinterleave_nxv8i16_nxv32i16:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z4.h, z2.h, z3.h
; SVE-NEXT:    uzp1 z5.h, z0.h, z1.h
; SVE-NEXT:    uzp2 z3.h, z2.h, z3.h
; SVE-NEXT:    uzp2 z6.h, z0.h, z1.h
; SVE-NEXT:    uzp1 z0.h, z5.h, z4.h
; SVE-NEXT:    uzp2 z2.h, z5.h, z4.h
; SVE-NEXT:    uzp1 z1.h, z6.h, z3.h
; SVE-NEXT:    uzp2 z3.h, z6.h, z3.h
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv8i16_nxv32i16:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.h - z3.h }, { z0.h - z3.h }
; SME2-NEXT:    ret
  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave4.nxv32i16(<vscale x 32 x i16> %vec)
  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval
}

define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv16i32(<vscale x 16 x i32> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4i32_nxv16i32:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z4.s, z2.s, z3.s
; SVE-NEXT:    uzp1 z5.s, z0.s, z1.s
; SVE-NEXT:    uzp2 z3.s, z2.s, z3.s
; SVE-NEXT:    uzp2 z6.s, z0.s, z1.s
; SVE-NEXT:    uzp1 z0.s, z5.s, z4.s
; SVE-NEXT:    uzp2 z2.s, z5.s, z4.s
; SVE-NEXT:    uzp1 z1.s, z6.s, z3.s
; SVE-NEXT:    uzp2 z3.s, z6.s, z3.s
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4i32_nxv16i32:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z0.s - z3.s }, { z0.s - z3.s }
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave4.nxv16i32(<vscale x 16 x i32> %vec)
  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval
}

define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv8i64(<vscale x 8 x i64> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2i64_nxv8i64:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z4.d, z2.d, z3.d
; SVE-NEXT:    uzp1 z5.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z3.d, z2.d, z3.d
; SVE-NEXT:    uzp2 z6.d, z0.d, z1.d
; SVE-NEXT:    uzp1 z0.d, z5.d, z4.d
; SVE-NEXT:    uzp2 z2.d, z5.d, z4.d
; SVE-NEXT:    uzp1 z1.d, z6.d, z3.d
; SVE-NEXT:    uzp2 z3.d, z6.d, z3.d
; SVE-NEXT:    ret
;
; SME2-ALL-LABEL: vector_deinterleave_nxv2i64_nxv8i64:
; SME2-ALL:       // %bb.0:
; SME2-ALL-NEXT:    uzp { z2.d, z3.d }, z2.d, z3.d
; SME2-ALL-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-ALL-NEXT:    uzp { z4.d, z5.d }, z0.d, z2.d
; SME2-ALL-NEXT:    uzp { z2.d, z3.d }, z1.d, z3.d
; SME2-ALL-NEXT:    mov z0.d, z4.d
; SME2-ALL-NEXT:    mov z1.d, z2.d
; SME2-ALL-NEXT:    mov z2.d, z5.d
; SME2-ALL-NEXT:    ret
;
; SME2-256-LABEL: vector_deinterleave_nxv2i64_nxv8i64:
; SME2-256:       // %bb.0:
; SME2-256-NEXT:    uzp { z0.d - z3.d }, { z0.d - z3.d }
; SME2-256-NEXT:    ret
  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %vec)
  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval
}

define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv16i64(<vscale x 16 x i64> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2i64_nxv16i64:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z24.d, z6.d, z7.d
; SVE-NEXT:    uzp1 z25.d, z4.d, z5.d
; SVE-NEXT:    uzp1 z26.d, z2.d, z3.d
; SVE-NEXT:    uzp1 z27.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z6.d, z6.d, z7.d
; SVE-NEXT:    uzp2 z4.d, z4.d, z5.d
; SVE-NEXT:    uzp2 z2.d, z2.d, z3.d
; SVE-NEXT:    uzp2 z0.d, z0.d, z1.d
; SVE-NEXT:    uzp1 z5.d, z25.d, z24.d
; SVE-NEXT:    uzp2 z24.d, z25.d, z24.d
; SVE-NEXT:    uzp1 z7.d, z27.d, z26.d
; SVE-NEXT:    uzp1 z28.d, z4.d, z6.d
; SVE-NEXT:    uzp2 z25.d, z27.d, z26.d
; SVE-NEXT:    uzp1 z29.d, z0.d, z2.d
; SVE-NEXT:    uzp2 z26.d, z4.d, z6.d
; SVE-NEXT:    uzp2 z27.d, z0.d, z2.d
; SVE-NEXT:    uzp1 z0.d, z7.d, z5.d
; SVE-NEXT:    uzp1 z2.d, z25.d, z24.d
; SVE-NEXT:    uzp2 z4.d, z7.d, z5.d
; SVE-NEXT:    uzp1 z1.d, z29.d, z28.d
; SVE-NEXT:    uzp1 z3.d, z27.d, z26.d
; SVE-NEXT:    uzp2 z5.d, z29.d, z28.d
; SVE-NEXT:    uzp2 z6.d, z25.d, z24.d
; SVE-NEXT:    uzp2 z7.d, z27.d, z26.d
; SVE-NEXT:    ret
;
; SME2-ALL-LABEL: vector_deinterleave_nxv2i64_nxv16i64:
; SME2-ALL:       // %bb.0:
; SME2-ALL-NEXT:    uzp { z6.d, z7.d }, z6.d, z7.d
; SME2-ALL-NEXT:    uzp { z4.d, z5.d }, z4.d, z5.d
; SME2-ALL-NEXT:    uzp { z24.d, z25.d }, z4.d, z6.d
; SME2-ALL-NEXT:    uzp { z2.d, z3.d }, z2.d, z3.d
; SME2-ALL-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-ALL-NEXT:    uzp { z28.d, z29.d }, z0.d, z2.d
; SME2-ALL-NEXT:    uzp { z26.d, z27.d }, z28.d, z24.d
; SME2-ALL-NEXT:    uzp { z6.d, z7.d }, z5.d, z7.d
; SME2-ALL-NEXT:    uzp { z0.d, z1.d }, z1.d, z3.d
; SME2-ALL-NEXT:    uzp { z4.d, z5.d }, z0.d, z6.d
; SME2-ALL-NEXT:    uzp { z24.d, z25.d }, z29.d, z25.d
; SME2-ALL-NEXT:    uzp { z6.d, z7.d }, z1.d, z7.d
; SME2-ALL-NEXT:    mov z0.d, z26.d
; SME2-ALL-NEXT:    mov z1.d, z4.d
; SME2-ALL-NEXT:    mov z2.d, z24.d
; SME2-ALL-NEXT:    mov z3.d, z6.d
; SME2-ALL-NEXT:    mov z4.d, z27.d
; SME2-ALL-NEXT:    mov z6.d, z25.d
; SME2-ALL-NEXT:    ret
;
; SME2-256-LABEL: vector_deinterleave_nxv2i64_nxv16i64:
; SME2-256:       // %bb.0:
; SME2-256-NEXT:    uzp { z4.d - z7.d }, { z4.d - z7.d }
; SME2-256-NEXT:    uzp { z0.d - z3.d }, { z0.d - z3.d }
; SME2-256-NEXT:    uzp { z26.d, z27.d }, z0.d, z4.d
; SME2-256-NEXT:    uzp { z4.d, z5.d }, z1.d, z5.d
; SME2-256-NEXT:    uzp { z24.d, z25.d }, z2.d, z6.d
; SME2-256-NEXT:    uzp { z6.d, z7.d }, z3.d, z7.d
; SME2-256-NEXT:    mov z0.d, z26.d
; SME2-256-NEXT:    mov z1.d, z4.d
; SME2-256-NEXT:    mov z2.d, z24.d
; SME2-256-NEXT:    mov z3.d, z6.d
; SME2-256-NEXT:    mov z4.d, z27.d
; SME2-256-NEXT:    mov z6.d, z25.d
; SME2-256-NEXT:    ret
  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave8.nxv16i64(<vscale x 16 x i64> %vec)
  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval
}

; Predicated
define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv32i1(<vscale x 32 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 p2.b, p0.b, p1.b
; CHECK-NEXT:    uzp2 p1.b, p0.b, p1.b
; CHECK-NEXT:    mov p0.b, p2.b
; CHECK-NEXT:    ret
  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
  ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
}

define {<vscale x 8 x i1>, <vscale x 8 x i1>} @vector_deinterleave_nxv8i1_nxv16i1(<vscale x 16 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8i1_nxv16i1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 p1.b, p0.b, p0.b
; CHECK-NEXT:    uzp2 p2.b, p0.b, p0.b
; CHECK-NEXT:    punpklo p0.h, p1.b
; CHECK-NEXT:    punpklo p1.h, p2.b
; CHECK-NEXT:    ret
  %retval = call {<vscale x 8 x i1>, <vscale x 8 x i1>} @llvm.vector.deinterleave2.nxv16i1(<vscale x 16 x i1> %vec)
  ret {<vscale x 8 x i1>, <vscale x 8 x i1>} %retval
}

define {<vscale x 4 x i1>, <vscale x 4 x i1>} @vector_deinterleave_nxv4i1_nxv8i1(<vscale x 8 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv4i1_nxv8i1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 p1.h, p0.h, p0.h
; CHECK-NEXT:    uzp2 p2.h, p0.h, p0.h
; CHECK-NEXT:    punpklo p0.h, p1.b
; CHECK-NEXT:    punpklo p1.h, p2.b
; CHECK-NEXT:    ret
  %retval = call {<vscale x 4 x i1>, <vscale x 4 x i1>} @llvm.vector.deinterleave2.nxv8i1(<vscale x 8 x i1> %vec)
  ret {<vscale x 4 x i1>, <vscale x 4 x i1>} %retval
}

define {<vscale x 2 x i1>, <vscale x 2 x i1>} @vector_deinterleave_nxv2i1_nxv4i1(<vscale x 4 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2i1_nxv4i1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 p1.s, p0.s, p0.s
; CHECK-NEXT:    uzp2 p2.s, p0.s, p0.s
; CHECK-NEXT:    punpklo p0.h, p1.b
; CHECK-NEXT:    punpklo p1.h, p2.b
; CHECK-NEXT:    ret
  %retval = call {<vscale x 2 x i1>, <vscale x 2 x i1>} @llvm.vector.deinterleave2.nxv4i1(<vscale x 4 x i1> %vec)
  ret {<vscale x 2 x i1>, <vscale x 2 x i1>} %retval
}


; Split illegal types

define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv8i64(<vscale x 8 x i64> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z4.d, z2.d, z3.d
; SVE-NEXT:    uzp1 z5.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z6.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z3.d, z2.d, z3.d
; SVE-NEXT:    mov z0.d, z5.d
; SVE-NEXT:    mov z1.d, z4.d
; SVE-NEXT:    mov z2.d, z6.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z4.d, z5.d }, z0.d, z1.d
; SME2-NEXT:    uzp { z2.d, z3.d }, z2.d, z3.d
; SME2-NEXT:    mov z0.d, z4.d
; SME2-NEXT:    mov z1.d, z2.d
; SME2-NEXT:    mov z2.d, z5.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
  ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
}

define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
; SVE-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
; SVE:       // %bb.0:
; SVE-NEXT:    uzp1 z24.d, z2.d, z3.d
; SVE-NEXT:    uzp1 z25.d, z0.d, z1.d
; SVE-NEXT:    uzp1 z26.d, z4.d, z5.d
; SVE-NEXT:    uzp1 z27.d, z6.d, z7.d
; SVE-NEXT:    uzp2 z28.d, z0.d, z1.d
; SVE-NEXT:    uzp2 z29.d, z2.d, z3.d
; SVE-NEXT:    uzp2 z30.d, z4.d, z5.d
; SVE-NEXT:    uzp2 z7.d, z6.d, z7.d
; SVE-NEXT:    mov z0.d, z25.d
; SVE-NEXT:    mov z1.d, z24.d
; SVE-NEXT:    mov z2.d, z26.d
; SVE-NEXT:    mov z3.d, z27.d
; SVE-NEXT:    mov z4.d, z28.d
; SVE-NEXT:    mov z5.d, z29.d
; SVE-NEXT:    mov z6.d, z30.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
; SME2:       // %bb.0:
; SME2-NEXT:    uzp { z24.d, z25.d }, z0.d, z1.d
; SME2-NEXT:    uzp { z26.d, z27.d }, z2.d, z3.d
; SME2-NEXT:    uzp { z28.d, z29.d }, z4.d, z5.d
; SME2-NEXT:    uzp { z6.d, z7.d }, z6.d, z7.d
; SME2-NEXT:    mov z0.d, z24.d
; SME2-NEXT:    mov z1.d, z26.d
; SME2-NEXT:    mov z2.d, z28.d
; SME2-NEXT:    mov z3.d, z6.d
; SME2-NEXT:    mov z4.d, z25.d
; SME2-NEXT:    mov z5.d, z27.d
; SME2-NEXT:    mov z6.d, z29.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
  ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
}


; Promote illegal type size

define {<vscale x 8 x i8>, <vscale x 8 x i8>} @vector_deinterleave_nxv8i8_nxv16i8(<vscale x 16 x i8> %vec) {
; SVE-LABEL: vector_deinterleave_nxv8i8_nxv16i8:
; SVE:       // %bb.0:
; SVE-NEXT:    uunpkhi z1.h, z0.b
; SVE-NEXT:    uunpklo z2.h, z0.b
; SVE-NEXT:    uzp1 z0.h, z2.h, z1.h
; SVE-NEXT:    uzp2 z1.h, z2.h, z1.h
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv8i8_nxv16i8:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.h, z0.b
; SME2-NEXT:    uunpklo z0.h, z0.b
; SME2-NEXT:    uzp { z0.h, z1.h }, z0.h, z1.h
; SME2-NEXT:    ret
  %retval = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %vec)
  ret {<vscale x 8 x i8>, <vscale x 8 x i8>} %retval
}

define {<vscale x 4 x i16>, <vscale x 4 x i16>} @vector_deinterleave_nxv4i16_nxv8i16(<vscale x 8 x i16> %vec) {
; SVE-LABEL: vector_deinterleave_nxv4i16_nxv8i16:
; SVE:       // %bb.0:
; SVE-NEXT:    uunpkhi z1.s, z0.h
; SVE-NEXT:    uunpklo z2.s, z0.h
; SVE-NEXT:    uzp1 z0.s, z2.s, z1.s
; SVE-NEXT:    uzp2 z1.s, z2.s, z1.s
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv4i16_nxv8i16:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.s, z0.h
; SME2-NEXT:    uunpklo z0.s, z0.h
; SME2-NEXT:    uzp { z0.s, z1.s }, z0.s, z1.s
; SME2-NEXT:    ret
  %retval = call {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.vector.deinterleave2.nxv8i16(<vscale x 8 x i16> %vec)
  ret {<vscale x 4 x i16>, <vscale x 4 x i16>} %retval
}

define {<vscale x 2 x i32>, <vscale x 2 x i32>} @vector_deinterleave_nxv2i32_nxv4i32(<vscale x 4 x i32> %vec) {
; SVE-LABEL: vector_deinterleave_nxv2i32_nxv4i32:
; SVE:       // %bb.0:
; SVE-NEXT:    uunpkhi z1.d, z0.s
; SVE-NEXT:    uunpklo z2.d, z0.s
; SVE-NEXT:    uzp1 z0.d, z2.d, z1.d
; SVE-NEXT:    uzp2 z1.d, z2.d, z1.d
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave_nxv2i32_nxv4i32:
; SME2:       // %bb.0:
; SME2-NEXT:    uunpkhi z1.d, z0.s
; SME2-NEXT:    uunpklo z0.d, z0.s
; SME2-NEXT:    uzp { z0.d, z1.d }, z0.d, z1.d
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %vec)
  ret {<vscale x 2 x i32>, <vscale x 2 x i32>} %retval
}


define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave6_nxv2i64_nxv12i64(<vscale x 12 x i64> %vec) {
; SVE-LABEL: vector_deinterleave6_nxv2i64_nxv12i64:
; SVE:       // %bb.0:
; SVE-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; SVE-NEXT:    addvl sp, sp, #-6
; SVE-NEXT:    .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
; SVE-NEXT:    .cfi_offset w29, -16
; SVE-NEXT:    ptrue p0.d
; SVE-NEXT:    str z5, [sp, #5, mul vl]
; SVE-NEXT:    str z4, [sp, #4, mul vl]
; SVE-NEXT:    str z3, [sp, #3, mul vl]
; SVE-NEXT:    str z2, [sp, #2, mul vl]
; SVE-NEXT:    str z1, [sp, #1, mul vl]
; SVE-NEXT:    str z0, [sp]
; SVE-NEXT:    ld3d { z5.d - z7.d }, p0/z, [sp, #3, mul vl]
; SVE-NEXT:    ld3d { z24.d - z26.d }, p0/z, [sp]
; SVE-NEXT:    uzp1 z0.d, z24.d, z5.d
; SVE-NEXT:    uzp1 z1.d, z25.d, z6.d
; SVE-NEXT:    uzp1 z2.d, z26.d, z7.d
; SVE-NEXT:    uzp2 z3.d, z24.d, z5.d
; SVE-NEXT:    uzp2 z4.d, z25.d, z6.d
; SVE-NEXT:    uzp2 z5.d, z26.d, z7.d
; SVE-NEXT:    addvl sp, sp, #6
; SVE-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; SVE-NEXT:    ret
;
; SME2-LABEL: vector_deinterleave6_nxv2i64_nxv12i64:
; SME2:       // %bb.0:
; SME2-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; SME2-NEXT:    addvl sp, sp, #-6
; SME2-NEXT:    .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
; SME2-NEXT:    .cfi_offset w29, -16
; SME2-NEXT:    ptrue p0.d
; SME2-NEXT:    str z5, [sp, #5, mul vl]
; SME2-NEXT:    str z4, [sp, #4, mul vl]
; SME2-NEXT:    str z3, [sp, #3, mul vl]
; SME2-NEXT:    str z2, [sp, #2, mul vl]
; SME2-NEXT:    str z1, [sp, #1, mul vl]
; SME2-NEXT:    str z0, [sp]
; SME2-NEXT:    ld3d { z3.d - z5.d }, p0/z, [sp, #3, mul vl]
; SME2-NEXT:    ld3d { z24.d - z26.d }, p0/z, [sp]
; SME2-NEXT:    uzp { z2.d, z3.d }, z24.d, z3.d
; SME2-NEXT:    uzp { z6.d, z7.d }, z25.d, z4.d
; SME2-NEXT:    uzp { z4.d, z5.d }, z26.d, z5.d
; SME2-NEXT:    mov z0.d, z2.d
; SME2-NEXT:    mov z1.d, z6.d
; SME2-NEXT:    mov z2.d, z4.d
; SME2-NEXT:    mov z4.d, z7.d
; SME2-NEXT:    addvl sp, sp, #6
; SME2-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; SME2-NEXT:    ret
  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave6.nxv12i64(<vscale x 12 x i64> %vec)
  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval
}