; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p3 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p3 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p3 -force-streaming < %s | FileCheck %s
;
; SVCVTB (SCVTFB / UCVTFB)
;

define <vscale x 8 x half> @scvtfb_f16_i8(<vscale x 16 x i8> %zn) {
; CHECK-LABEL: scvtfb_f16_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf z0.h, z0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.nxv8f16.nxv16i8(<vscale x 16 x i8> %zn)
  ret <vscale x 8 x half> %res
}

define <vscale x 4 x float> @scvtfb_f32_i16(<vscale x 8 x i16> %zn) {
; CHECK-LABEL: scvtfb_f32_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf z0.s, z0.h
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.nxv4f32.nxv8i16(<vscale x 8 x i16> %zn)
  ret <vscale x 4 x float> %res
}

define <vscale x 2 x double> @scvtfb_f64_i32(<vscale x 4 x i32> %zn) {
; CHECK-LABEL: scvtfb_f64_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf z0.d, z0.s
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.nxv2f64.nxv4i32(<vscale x 4 x i32> %zn)
  ret <vscale x 2 x double> %res
}

define <vscale x 8 x half> @ucvtfb_f16_i8(<vscale x 16 x i8> %zn) {
; CHECK-LABEL: ucvtfb_f16_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf z0.h, z0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.nxv8f16.nxv16i8(<vscale x 16 x i8> %zn)
  ret <vscale x 8 x half> %res
}

define <vscale x 4 x float> @ucvtfb_f32_i16(<vscale x 8 x i16> %zn) {
; CHECK-LABEL: ucvtfb_f32_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf z0.s, z0.h
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.nxv4f32.nxv8i16(<vscale x 8 x i16> %zn)
  ret <vscale x 4 x float> %res
}

define <vscale x 2 x double> @ucvtfb_f64_i32(<vscale x 4 x i32> %zn) {
; CHECK-LABEL: ucvtfb_f64_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf z0.d, z0.s
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.nxv2f64.nxv4i32(<vscale x 4 x i32> %zn)
  ret <vscale x 2 x double> %res
}

;
; SVCVTT (SCVTFLT / UCVTFLT)
;

define <vscale x 8 x half> @scvtflt_f16_i8(<vscale x 16 x i8> %zn) {
; CHECK-LABEL: scvtflt_f16_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtflt z0.h, z0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x half> @llvm.aarch64.sve.scvtft.nxv8f16.nxv16i8(<vscale x 16 x i8> %zn)
  ret <vscale x 8 x half> %res
}

define <vscale x 4 x float> @scvtflt_f32_i16(<vscale x 8 x i16> %zn) {
; CHECK-LABEL: scvtflt_f32_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtflt z0.s, z0.h
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x float> @llvm.aarch64.sve.scvtft.nxv4f32.nxv8i16(<vscale x 8 x i16> %zn)
  ret <vscale x 4 x float> %res
}

define <vscale x 2 x double> @scvtflt_f64_i32(<vscale x 4 x i32> %zn) {
; CHECK-LABEL: scvtflt_f64_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtflt z0.d, z0.s
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x double> @llvm.aarch64.sve.scvtft.nxv2f64.nxv4i32(<vscale x 4 x i32> %zn)
  ret <vscale x 2 x double> %res
}

define <vscale x 8 x half> @ucvtflt_f16_i8(<vscale x 16 x i8> %zn) {
; CHECK-LABEL: ucvtflt_f16_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtflt z0.h, z0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtft.nxv8f16.nxv16i8(<vscale x 16 x i8> %zn)
  ret <vscale x 8 x half> %res
}

define <vscale x 4 x float> @ucvtflt_f32_i16(<vscale x 8 x i16> %zn) {
; CHECK-LABEL: ucvtflt_f32_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtflt z0.s, z0.h
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtft.nxv4f32.nxv8i16(<vscale x 8 x i16> %zn)
  ret <vscale x 4 x float> %res
}

define <vscale x 2 x double> @ucvtflt_f64_i32(<vscale x 4 x i32> %zn) {
; CHECK-LABEL: ucvtflt_f64_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtflt z0.d, z0.s
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtft.nxv2f64.nxv4i32(<vscale x 4 x i32> %zn)
  ret <vscale x 2 x double> %res
}