; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -stop-after=instruction-select < %s | FileCheck %s --check-prefixes=GFX10

; --- atomicrmw fmax: global f32/f64, flat f32/f64, local f32/f64 ---

define void @atomicrmw_fmax_global_f32_vv_noret(ptr addrspace(1) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_global_f32_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   GLOBAL_ATOMIC_FMAX [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmax ptr addrspace(1) %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define float @atomicrmw_fmax_global_f32_vv_ret(ptr addrspace(1) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_global_f32_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[GLOBAL_ATOMIC_FMAX_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_FMAX_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   $vgpr0 = COPY [[GLOBAL_ATOMIC_FMAX_RTN]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0
  %old = atomicrmw fmax ptr addrspace(1) %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret float %old
}

define void @atomicrmw_fmax_global_f64_vv_noret(ptr addrspace(1) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_global_f64_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   GLOBAL_ATOMIC_MAX_F64 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmax ptr addrspace(1) %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define double @atomicrmw_fmax_global_f64_vv_ret(ptr addrspace(1) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_global_f64_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   [[GLOBAL_ATOMIC_MAX_F64_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_MAX_F64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 1, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_ATOMIC_MAX_F64_RTN]].sub0
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_ATOMIC_MAX_F64_RTN]].sub1
  ; GFX10-NEXT:   $vgpr0 = COPY [[COPY4]]
  ; GFX10-NEXT:   $vgpr1 = COPY [[COPY5]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
  %old = atomicrmw fmax ptr addrspace(1) %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret double %old
}

define void @atomicrmw_fmax_flat_f32_vv_noret(ptr %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_flat_f32_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   FLAT_ATOMIC_FMAX [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst (s32) on %ir.ptr)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmax ptr %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define float @atomicrmw_fmax_flat_f32_vv_ret(ptr %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_flat_f32_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[FLAT_ATOMIC_FMAX_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_FMAX_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store seq_cst (s32) on %ir.ptr)
  ; GFX10-NEXT:   $vgpr0 = COPY [[FLAT_ATOMIC_FMAX_RTN]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0
  %old = atomicrmw fmax ptr %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret float %old
}

define void @atomicrmw_fmax_flat_f64_vv_noret(ptr %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_flat_f64_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX10-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2.Flow:
  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3.atomicrmw.private:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
  ; GFX10-NEXT:   [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
  ; GFX10-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX10-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.7, align 8, addrspace 5)
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.7 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
  ; GFX10-NEXT:   [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MAX_F64_e64_2:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub0
  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub1
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.7, align 8, addrspace 5)
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.7 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   S_BRANCH %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4.atomicrmw.global:
  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   FLAT_ATOMIC_MAX_F64 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst (s64) on %ir.ptr, !noalias.addrspace !1)
  ; GFX10-NEXT:   S_BRANCH %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5.atomicrmw.phi:
  ; GFX10-NEXT:   SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmax ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define double @atomicrmw_fmax_flat_f64_vv_ret(ptr %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_flat_f64_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX10-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2.Flow:
  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI %19, %bb.4, [[DEF]], %bb.1
  ; GFX10-NEXT:   [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3.atomicrmw.private:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
  ; GFX10-NEXT:   [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
  ; GFX10-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX10-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.8, align 8, addrspace 5)
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.8 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
  ; GFX10-NEXT:   [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MAX_F64_e64_2:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub0
  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub1
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.8, align 8, addrspace 5)
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.8 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   S_BRANCH %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4.atomicrmw.global:
  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[FLAT_ATOMIC_MAX_F64_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_MAX_F64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 1, implicit $exec, implicit $flat_scr :: (load store seq_cst (s64) on %ir.ptr, !noalias.addrspace !1)
  ; GFX10-NEXT:   S_BRANCH %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5.atomicrmw.phi:
  ; GFX10-NEXT:   successors: %bb.6(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:vreg_64 = PHI [[PHI]], %bb.2, [[REG_SEQUENCE2]], %bb.3
  ; GFX10-NEXT:   SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.6.atomicrmw.end:
  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub1
  ; GFX10-NEXT:   $vgpr0 = COPY [[COPY13]]
  ; GFX10-NEXT:   $vgpr1 = COPY [[COPY14]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
  %old = atomicrmw fmax ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret double %old
}

define void @atomicrmw_fmax_local_f32_vv_noret(ptr addrspace(3) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_local_f32_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   DS_MAX_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmax ptr addrspace(3) %ptr, float %val seq_cst
  ret void
}

define float @atomicrmw_fmax_local_f32_vv_ret(ptr addrspace(3) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_local_f32_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[DS_MAX_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MAX_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   $vgpr0 = COPY [[DS_MAX_RTN_F32_gfx9_]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0
  %old = atomicrmw fmax ptr addrspace(3) %ptr, float %val seq_cst
  ret float %old
}

define void @atomicrmw_fmax_local_f64_vv_noret(ptr addrspace(3) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_local_f64_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
  ; GFX10-NEXT:   DS_MAX_F64_gfx9 [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmax ptr addrspace(3) %ptr, double %val seq_cst
  ret void
}

define double @atomicrmw_fmax_local_f64_vv_ret(ptr addrspace(3) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmax_local_f64_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
  ; GFX10-NEXT:   [[DS_MAX_RTN_F64_gfx9_:%[0-9]+]]:vreg_64 = DS_MAX_RTN_F64_gfx9 [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DS_MAX_RTN_F64_gfx9_]].sub0
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[DS_MAX_RTN_F64_gfx9_]].sub1
  ; GFX10-NEXT:   $vgpr0 = COPY [[COPY3]]
  ; GFX10-NEXT:   $vgpr1 = COPY [[COPY4]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
  %old = atomicrmw fmax ptr addrspace(3) %ptr, double %val seq_cst
  ret double %old
}

; --- atomicrmw fmin: global f32/f64, flat f32/f64, local f32/f64 ---

define void @atomicrmw_fmin_global_f32_vv_noret(ptr addrspace(1) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_global_f32_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   GLOBAL_ATOMIC_FMIN [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmin ptr addrspace(1) %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define float @atomicrmw_fmin_global_f32_vv_ret(ptr addrspace(1) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_global_f32_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[GLOBAL_ATOMIC_FMIN_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_FMIN_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   $vgpr0 = COPY [[GLOBAL_ATOMIC_FMIN_RTN]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0
  %old = atomicrmw fmin ptr addrspace(1) %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret float %old
}

define void @atomicrmw_fmin_global_f64_vv_noret(ptr addrspace(1) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_global_f64_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   GLOBAL_ATOMIC_MIN_F64 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmin ptr addrspace(1) %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define double @atomicrmw_fmin_global_f64_vv_ret(ptr addrspace(1) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_global_f64_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   [[GLOBAL_ATOMIC_MIN_F64_RTN:%[0-9]+]]:vreg_64 = GLOBAL_ATOMIC_MIN_F64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 1, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 1)
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_ATOMIC_MIN_F64_RTN]].sub0
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_ATOMIC_MIN_F64_RTN]].sub1
  ; GFX10-NEXT:   $vgpr0 = COPY [[COPY4]]
  ; GFX10-NEXT:   $vgpr1 = COPY [[COPY5]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
  %old = atomicrmw fmin ptr addrspace(1) %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret double %old
}

define void @atomicrmw_fmin_flat_f32_vv_noret(ptr %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_flat_f32_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   FLAT_ATOMIC_FMIN [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst (s32) on %ir.ptr)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmin ptr %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define float @atomicrmw_fmin_flat_f32_vv_ret(ptr %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_flat_f32_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[FLAT_ATOMIC_FMIN_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_FMIN_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store seq_cst (s32) on %ir.ptr)
  ; GFX10-NEXT:   $vgpr0 = COPY [[FLAT_ATOMIC_FMIN_RTN]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0
  %old = atomicrmw fmin ptr %ptr, float %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret float %old
}

define void @atomicrmw_fmin_flat_f64_vv_noret(ptr %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_flat_f64_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX10-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2.Flow:
  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3.atomicrmw.private:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
  ; GFX10-NEXT:   [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
  ; GFX10-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX10-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.7, align 8, addrspace 5)
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.7 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
  ; GFX10-NEXT:   [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MIN_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub0
  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub1
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.7, align 8, addrspace 5)
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.7 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   S_BRANCH %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4.atomicrmw.global:
  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   FLAT_ATOMIC_MIN_F64 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec, implicit $flat_scr :: (load store seq_cst (s64) on %ir.ptr, !noalias.addrspace !1)
  ; GFX10-NEXT:   S_BRANCH %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5.atomicrmw.phi:
  ; GFX10-NEXT:   SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmin ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret void
}

define double @atomicrmw_fmin_flat_f64_vv_ret(ptr %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_flat_f64_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GFX10-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
  ; GFX10-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2.Flow:
  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI %19, %bb.4, [[DEF]], %bb.1
  ; GFX10-NEXT:   [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec = SI_ELSE [[SI_IF]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   S_BRANCH %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3.atomicrmw.private:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
  ; GFX10-NEXT:   [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
  ; GFX10-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
  ; GFX10-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.8, align 8, addrspace 5)
  ; GFX10-NEXT:   [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.8 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
  ; GFX10-NEXT:   [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[V_MIN_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub0
  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub1
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.8, align 8, addrspace 5)
  ; GFX10-NEXT:   BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.8 + 4, basealign 8, addrspace 5)
  ; GFX10-NEXT:   S_BRANCH %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4.atomicrmw.global:
  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[FLAT_ATOMIC_MIN_F64_RTN:%[0-9]+]]:vreg_64 = FLAT_ATOMIC_MIN_F64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 1, implicit $exec, implicit $flat_scr :: (load store seq_cst (s64) on %ir.ptr, !noalias.addrspace !1)
  ; GFX10-NEXT:   S_BRANCH %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5.atomicrmw.phi:
  ; GFX10-NEXT:   successors: %bb.6(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:vreg_64 = PHI [[PHI]], %bb.2, [[REG_SEQUENCE2]], %bb.3
  ; GFX10-NEXT:   SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.6.atomicrmw.end:
  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub1
  ; GFX10-NEXT:   $vgpr0 = COPY [[COPY13]]
  ; GFX10-NEXT:   $vgpr1 = COPY [[COPY14]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
  %old = atomicrmw fmin ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
  ret double %old
}

define void @atomicrmw_fmin_local_f32_vv_noret(ptr addrspace(3) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_local_f32_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   DS_MIN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmin ptr addrspace(3) %ptr, float %val seq_cst
  ret void
}

define float @atomicrmw_fmin_local_f32_vv_ret(ptr addrspace(3) %ptr, float %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_local_f32_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[DS_MIN_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_MIN_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst (s32) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   $vgpr0 = COPY [[DS_MIN_RTN_F32_gfx9_]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0
  %old = atomicrmw fmin ptr addrspace(3) %ptr, float %val seq_cst
  ret float %old
}

define void @atomicrmw_fmin_local_f64_vv_noret(ptr addrspace(3) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_local_f64_vv_noret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
  ; GFX10-NEXT:   DS_MIN_F64_gfx9 [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   SI_RETURN
  %old = atomicrmw fmin ptr addrspace(3) %ptr, double %val seq_cst
  ret void
}

define double @atomicrmw_fmin_local_f64_vv_ret(ptr addrspace(3) %ptr, double %val) {
  ; GFX10-LABEL: name: atomicrmw_fmin_local_f64_vv_ret
  ; GFX10: bb.1 (%ir-block.0):
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GFX10-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
  ; GFX10-NEXT:   [[DS_MIN_RTN_F64_gfx9_:%[0-9]+]]:vreg_64 = DS_MIN_RTN_F64_gfx9 [[COPY]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store seq_cst (s64) on %ir.ptr, addrspace 3)
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DS_MIN_RTN_F64_gfx9_]].sub0
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[DS_MIN_RTN_F64_gfx9_]].sub1
  ; GFX10-NEXT:   $vgpr0 = COPY [[COPY3]]
  ; GFX10-NEXT:   $vgpr1 = COPY [[COPY4]]
  ; GFX10-NEXT:   SI_RETURN implicit $vgpr0, implicit $vgpr1
  %old = atomicrmw fmin ptr addrspace(3) %ptr, double %val seq_cst
  ret double %old
}

!0 = !{}