; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 %s -o - | FileCheck -check-prefix=GCN %s

define amdgpu_cs float @div_sqrt(float inreg %arg1) {
; GCN-LABEL: div_sqrt:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_mul_f32_e64 v0, 0x4f800000, s0
; GCN-NEXT:    v_cmp_gt_f32_e64 s1, 0xf800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s2, v0
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    s_cselect_b32 s1, 1, 0
; GCN-NEXT:    s_cselect_b32 s2, s2, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s2
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s2
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s2
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s2, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s2, s0
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = call float @llvm.sqrt.f32(float %arg1)
  %b = fdiv afn float 1.000000e+00, %a
  ret float %b
}

define amdgpu_cs float @sqrt_div(float inreg %arg1) {
; GCN-LABEL: sqrt_div:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; GCN-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
; GCN-NEXT:    v_readfirstlane_b32 s0, v0
; GCN-NEXT:    v_readfirstlane_b32 s1, v1
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s2, 1, 0
; GCN-NEXT:    s_cselect_b32 s1, s1, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s1
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s1
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s1
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s1, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s2, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s1, s0
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = fdiv afn float 1.000000e+00, %arg1
  %b = call float @llvm.sqrt.f32(float %a)
  ret float %b
}

define amdgpu_cs float @rcp_sqrt(float inreg %arg1) {
; GCN-LABEL: rcp_sqrt:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_mul_f32_e64 v0, 0x4f800000, s0
; GCN-NEXT:    v_cmp_gt_f32_e64 s1, 0xf800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s2, v0
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    s_cselect_b32 s1, 1, 0
; GCN-NEXT:    s_cselect_b32 s2, s2, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s2
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s2
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s2
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s2, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s2, s0
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = call float @llvm.sqrt.f32(float %arg1)
  %b = call float @llvm.amdgcn.rcp.f32(float %a)
  ret float %b
}

define amdgpu_cs float @sqrt_rcp(float inreg %arg1) {
; GCN-LABEL: sqrt_rcp:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; GCN-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
; GCN-NEXT:    v_readfirstlane_b32 s0, v0
; GCN-NEXT:    v_readfirstlane_b32 s1, v1
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s2, 1, 0
; GCN-NEXT:    s_cselect_b32 s1, s1, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s1
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s1
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s1
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s1, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s2, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s1, s0
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = call float @llvm.amdgcn.rcp.f32(float %arg1)
  %b = call float @llvm.sqrt.f32(float %a)
  ret float %b
}

define amdgpu_cs float @div_sqrt_contract(float inreg %arg1) {
; GCN-LABEL: div_sqrt_contract:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_mul_f32_e64 v0, 0x4f800000, s0
; GCN-NEXT:    v_cmp_gt_f32_e64 s1, 0xf800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s2, v0
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    s_cselect_b32 s1, 1, 0
; GCN-NEXT:    s_cselect_b32 s2, s2, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s2
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s2
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s2
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s2, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s2, s0
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = call contract float @llvm.sqrt.f32(float %arg1)
  %b = fdiv afn contract float 1.000000e+00, %a
  ret float %b
}

define amdgpu_cs float @sqrt_div_contract(float inreg %arg1) {
; GCN-LABEL: sqrt_div_contract:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; GCN-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
; GCN-NEXT:    v_readfirstlane_b32 s0, v0
; GCN-NEXT:    v_readfirstlane_b32 s1, v1
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s2, 1, 0
; GCN-NEXT:    s_cselect_b32 s1, s1, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s1
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s1
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s1
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s1, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s2, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s1, s0
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = fdiv afn contract float 1.000000e+00, %arg1
  %b = call contract float @llvm.sqrt.f32(float %a)
  ret float %b
}

define amdgpu_cs float @rcp_sqrt_contract(float inreg %arg1) {
; GCN-LABEL: rcp_sqrt_contract:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_mul_f32_e64 v0, 0x4f800000, s0
; GCN-NEXT:    v_cmp_gt_f32_e64 s1, 0xf800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s2, v0
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    s_cselect_b32 s1, 1, 0
; GCN-NEXT:    s_cselect_b32 s2, s2, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s2
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s2
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s2
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s2, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s1, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s2, s0
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = call contract float @llvm.sqrt.f32(float %arg1)
  %b = call contract float @llvm.amdgcn.rcp.f32(float %a)
  ret float %b
}

define amdgpu_cs float @sqrt_rcp_contract(float inreg %arg1) {
; GCN-LABEL: sqrt_rcp_contract:
; GCN:       ; %bb.0: ; %.entry
; GCN-NEXT:    v_rcp_f32_e32 v0, s0
; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
; GCN-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
; GCN-NEXT:    v_readfirstlane_b32 s0, v0
; GCN-NEXT:    v_readfirstlane_b32 s1, v1
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s2, 1, 0
; GCN-NEXT:    s_cselect_b32 s1, s1, s0
; GCN-NEXT:    v_sqrt_f32_e32 v0, s1
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_add_i32 s4, s3, -1
; GCN-NEXT:    s_add_i32 s5, s3, 1
; GCN-NEXT:    v_fma_f32 v1, -s4, v0, s1
; GCN-NEXT:    v_fma_f32 v0, -s5, v0, s1
; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
; GCN-NEXT:    v_cmp_lt_f32_e64 s0, 0, v0
; GCN-NEXT:    s_cmp_lg_u32 vcc_lo, 0
; GCN-NEXT:    s_cselect_b32 s3, s4, s3
; GCN-NEXT:    s_cmp_lg_u32 s0, 0
; GCN-NEXT:    v_cmp_class_f32_e64 s4, s1, 0x260
; GCN-NEXT:    s_cselect_b32 s0, s5, s3
; GCN-NEXT:    s_cmp_lg_u32 s2, 0
; GCN-NEXT:    v_mul_f32_e64 v0, 0x37800000, s0
; GCN-NEXT:    v_readfirstlane_b32 s3, v0
; GCN-NEXT:    s_cselect_b32 s0, s3, s0
; GCN-NEXT:    s_cmp_lg_u32 s4, 0
; GCN-NEXT:    s_cselect_b32 s0, s1, s0
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
.entry:
  %a = call contract float @llvm.amdgcn.rcp.f32(float %arg1)
  %b = call contract float @llvm.sqrt.f32(float %a)
  ret float %b
}

declare float @llvm.sqrt.f32(float)
declare float @llvm.amdgcn.rcp.f32(float)