; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii -stop-after=instruction-select < %s | FileCheck -check-prefix=GCN %s

define amdgpu_ps float @strictwqm_f32(float %val) {
  ; GCN-LABEL: name: strictwqm_f32
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $vgpr0
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN-NEXT:   early-clobber %2:vgpr_32 = STRICT_WQM [[COPY]], implicit $exec
  ; GCN-NEXT:   $vgpr0 = COPY %2
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
  %ret = call float @llvm.amdgcn.strict.wqm.f32(float %val)
  ret float %ret
}

define amdgpu_ps float @s_strictwqm_f32(float inreg %val) {
  ; GCN-LABEL: name: s_strictwqm_f32
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $sgpr0
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN-NEXT:   early-clobber %2:sreg_32 = STRICT_WQM [[COPY]], implicit $exec
  ; GCN-NEXT:   $vgpr0 = COPY %2
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
  %ret = call float @llvm.amdgcn.strict.wqm.f32(float %val)
  ret float %ret
}

define amdgpu_ps float @strictwqm_v2f16(float %arg) {
  ; GCN-LABEL: name: strictwqm_v2f16
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $vgpr0
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN-NEXT:   early-clobber %3:vgpr_32 = STRICT_WQM [[COPY]], implicit $exec
  ; GCN-NEXT:   $vgpr0 = COPY %3
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
  %val = bitcast float %arg to <2 x half>
  %ret = call <2 x half> @llvm.amdgcn.strict.wqm.v2f16(<2 x half> %val)
  %bc = bitcast <2 x half> %ret to float
  ret float %bc
}

define amdgpu_ps float @s_strictwqm_v2f16(float inreg %arg) {
  ; GCN-LABEL: name: s_strictwqm_v2f16
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $sgpr0
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN-NEXT:   early-clobber %3:sreg_32 = STRICT_WQM [[COPY]], implicit $exec
  ; GCN-NEXT:   $vgpr0 = COPY %3
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
  %val = bitcast float %arg to <2 x half>
  %ret = call <2 x half> @llvm.amdgcn.strict.wqm.v2f16(<2 x half> %val)
  %bc = bitcast <2 x half> %ret to float
  ret float %bc
}

define amdgpu_ps <2 x float> @strictwqm_f64(double %val) {
  ; GCN-LABEL: name: strictwqm_f64
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $vgpr0, $vgpr1
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GCN-NEXT:   early-clobber %4:vreg_64 = STRICT_WQM [[REG_SEQUENCE]], implicit $exec
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY %4.sub0
  ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY %4.sub1
  ; GCN-NEXT:   $vgpr0 = COPY [[COPY2]]
  ; GCN-NEXT:   $vgpr1 = COPY [[COPY3]]
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  %ret = call double @llvm.amdgcn.strict.wqm.f64(double %val)
  %bitcast = bitcast double %ret to <2 x float>
  ret <2 x float> %bitcast
}

define amdgpu_ps <2 x float> @s_strictwqm_f64(double inreg %val) {
  ; GCN-LABEL: name: s_strictwqm_f64
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  ; GCN-NEXT:   early-clobber %4:sreg_64 = STRICT_WQM [[REG_SEQUENCE]], implicit $exec
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY %4.sub0
  ; GCN-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY %4.sub1
  ; GCN-NEXT:   $vgpr0 = COPY [[COPY2]]
  ; GCN-NEXT:   $vgpr1 = COPY [[COPY3]]
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
  %ret = call double @llvm.amdgcn.strict.wqm.f64(double %val)
  %bitcast = bitcast double %ret to <2 x float>
  ret <2 x float> %bitcast
}

define amdgpu_ps <3 x float> @strictwqm_v3f32(<3 x float> %val) {
  ; GCN-LABEL: name: strictwqm_v3f32
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
  ; GCN-NEXT:   early-clobber %5:vreg_96 = STRICT_WQM [[REG_SEQUENCE]], implicit $exec
  ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub0
  ; GCN-NEXT:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY %5.sub1
  ; GCN-NEXT:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY %5.sub2
  ; GCN-NEXT:   $vgpr0 = COPY [[COPY3]]
  ; GCN-NEXT:   $vgpr1 = COPY [[COPY4]]
  ; GCN-NEXT:   $vgpr2 = COPY [[COPY5]]
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  %ret = call <3 x float> @llvm.amdgcn.strict.wqm.v3f32(<3 x float> %val)
  ret <3 x float> %ret
}

define amdgpu_ps <3 x float> @s_strictwqm_v3f32(<3 x float> inreg %val) {
  ; GCN-LABEL: name: s_strictwqm_v3f32
  ; GCN: bb.1 (%ir-block.0):
  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
  ; GCN-NEXT:   early-clobber %5:sgpr_96 = STRICT_WQM [[REG_SEQUENCE]], implicit $exec
  ; GCN-NEXT:   [[COPY3:%[0-9]+]]:sreg_32 = COPY %5.sub0
  ; GCN-NEXT:   [[COPY4:%[0-9]+]]:sreg_32 = COPY %5.sub1
  ; GCN-NEXT:   [[COPY5:%[0-9]+]]:sreg_32 = COPY %5.sub2
  ; GCN-NEXT:   $vgpr0 = COPY [[COPY3]]
  ; GCN-NEXT:   $vgpr1 = COPY [[COPY4]]
  ; GCN-NEXT:   $vgpr2 = COPY [[COPY5]]
  ; GCN-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
  %ret = call <3 x float> @llvm.amdgcn.strict.wqm.v3f32(<3 x float> %val)
  ret <3 x float> %ret
}

declare float @llvm.amdgcn.strict.wqm.f32(float) #0
declare <2 x half> @llvm.amdgcn.strict.wqm.v2f16(<2 x half>) #0
declare <3 x float> @llvm.amdgcn.strict.wqm.v3f32(<3 x float>) #0
declare double @llvm.amdgcn.strict.wqm.f64(double) #0

attributes #0 = { nounwind readnone speculatable }