; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s

define amdgpu_ps i32 @test_global_p1_s32_uniform(ptr addrspace(1) inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_global_p1_s32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_mov_b32 s4, s3
; GFX9-NEXT:    s_mov_b32 s5, s2
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(1) %ptr, i32 %cmp, i32 %new seq_cst seq_cst
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i32 @test_global_p1_s32_divergent(ptr addrspace(1) %ptr, i32 %cmp, i32 %new) {
; GFX9-LABEL: test_global_p1_s32_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v4, v2
; GFX9-NEXT:    global_atomic_cmpswap v0, v[0:1], v[3:4], off glc
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(1) %ptr, i32 %cmp, i32 %new seq_cst seq_cst
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i64 @test_global_p1_s64_uniform(ptr addrspace(1) inreg %ptr, i64 inreg %cmp, i64 inreg %new) {
; GFX9-LABEL: test_global_p1_s64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_mov_b32 s6, s2
; GFX9-NEXT:    s_mov_b32 s7, s3
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    v_mov_b32_e32 v2, s6
; GFX9-NEXT:    v_mov_b32_e32 v3, s7
; GFX9-NEXT:    v_mov_b32_e32 v4, 0
; GFX9-NEXT:    global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[0:1] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(1) %ptr, i64 %cmp, i64 %new seq_cst seq_cst
  %val = extractvalue { i64, i1 } %result, 0
  ret i64 %val
}

define amdgpu_ps i64 @test_global_p1_s64_divergent(ptr addrspace(1) %ptr, i64 %cmp, i64 %new) {
; GFX9-LABEL: test_global_p1_s64_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v6, v0
; GFX9-NEXT:    v_mov_b32_e32 v7, v1
; GFX9-NEXT:    v_mov_b32_e32 v0, v4
; GFX9-NEXT:    v_mov_b32_e32 v1, v5
; GFX9-NEXT:    global_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3], off glc
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(1) %ptr, i64 %cmp, i64 %new seq_cst seq_cst
  %val = extractvalue { i64, i1 } %result, 0
  ret i64 %val
}

define amdgpu_ps i32 @test_flat_p0_s32_uniform(ptr inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_flat_p0_s32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_mov_b32 s4, s3
; GFX9-NEXT:    s_mov_b32 s5, s2
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v3, s5
; GFX9-NEXT:    flat_atomic_cmpswap v0, v[0:1], v[2:3] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i32 @test_flat_p0_s32_divergent(ptr %ptr, i32 %cmp, i32 %new) {
; GFX9-LABEL: test_flat_p0_s32_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v4, v2
; GFX9-NEXT:    flat_atomic_cmpswap v0, v[0:1], v[3:4] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i32 @test_flat_p0_s32_uniform_noalias_private(ptr inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_flat_p0_s32_uniform_noalias_private:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_mov_b32 s4, s3
; GFX9-NEXT:    s_mov_b32 s5, s2
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v3, s5
; GFX9-NEXT:    flat_atomic_cmpswap v0, v[0:1], v[2:3] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst, !noalias.addrspace !0
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i32 @test_flat_p0_s32_divergent_noalias_private(ptr %ptr, i32 %cmp, i32 %new) {
; GFX9-LABEL: test_flat_p0_s32_divergent_noalias_private:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v4, v2
; GFX9-NEXT:    flat_atomic_cmpswap v0, v[0:1], v[3:4] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst, !noalias.addrspace !0
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

; TODO: Enable these two tests after G_PHI support.
; define amdgpu_ps i64 @test_flat_p0_s64_uniform(ptr inreg %ptr, i64 inreg %cmp, i64 inreg %new) {
;   %result = cmpxchg ptr %ptr, i64 %cmp, i64 %new seq_cst seq_cst
;   %val = extractvalue { i64, i1 } %result, 0
;   ret i64 %val
; }
;
; define amdgpu_ps i64 @test_flat_p0_s64_divergent(ptr %ptr, i64 %cmp, i64 %new) {
;   %result = cmpxchg ptr %ptr, i64 %cmp, i64 %new seq_cst seq_cst
;   %val = extractvalue { i64, i1 } %result, 0
;   ret i64 %val
; }

define amdgpu_ps i64 @test_flat_p0_s64_uniform_noalias_private(ptr inreg %ptr, i64 inreg %cmp, i64 inreg %new) {
; GFX9-LABEL: test_flat_p0_s64_uniform_noalias_private:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_mov_b32 s6, s2
; GFX9-NEXT:    s_mov_b32 s7, s3
; GFX9-NEXT:    v_mov_b32_e32 v5, s1
; GFX9-NEXT:    v_mov_b32_e32 v0, s4
; GFX9-NEXT:    v_mov_b32_e32 v4, s0
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    v_mov_b32_e32 v2, s6
; GFX9-NEXT:    v_mov_b32_e32 v3, s7
; GFX9-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr %ptr, i64 %cmp, i64 %new seq_cst seq_cst, !noalias.addrspace !0
  %val = extractvalue { i64, i1 } %result, 0
  ret i64 %val
}

define amdgpu_ps i64 @test_flat_p0_s64_divergent_noalias_private(ptr %ptr, i64 %cmp, i64 %new) {
; GFX9-LABEL: test_flat_p0_s64_divergent_noalias_private:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v6, v0
; GFX9-NEXT:    v_mov_b32_e32 v7, v1
; GFX9-NEXT:    v_mov_b32_e32 v0, v4
; GFX9-NEXT:    v_mov_b32_e32 v1, v5
; GFX9-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr %ptr, i64 %cmp, i64 %new seq_cst seq_cst, !noalias.addrspace !0
  %val = extractvalue { i64, i1 } %result, 0
  ret i64 %val
}

define amdgpu_kernel void @test_region_p2_s32_uniform(ptr addrspace(2) %gds, i32 %cmp, i32 %new) #0 {
; GFX9-LABEL: test_region_p2_s32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    ds_cmpst_b32 v0, v1, v2 gds
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    s_endpgm
  %result = cmpxchg ptr addrspace(2) %gds, i32 %cmp, i32 %new seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @test_region_p2_s32_divergent(ptr addrspace(2) %gds_base, i32 %cmp, i32 %new) #0 {
; GFX9-LABEL: test_region_p2_s32_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_add_u32_e32 v0, s0, v0
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    ds_cmpst_b32 v0, v1, v2 gds
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    s_endpgm
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %gds_ptr = getelementptr i32, ptr addrspace(2) %gds_base, i32 %tid
  %result = cmpxchg ptr addrspace(2) %gds_ptr, i32 %cmp, i32 %new seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @test_region_p2_s64_uniform(ptr addrspace(2) %gds, i64 %cmp, i64 %new) #0 {
; GFX9-LABEL: test_region_p2_s64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x24
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v4, s6
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v3, s3
; GFX9-NEXT:    ds_cmpst_b64 v4, v[0:1], v[2:3] gds
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    s_endpgm
  %result = cmpxchg ptr addrspace(2) %gds, i64 %cmp, i64 %new seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @test_region_p2_s64_divergent(ptr addrspace(2) %gds_base, i64 %cmp, i64 %new) #0 {
; GFX9-LABEL: test_region_p2_s64_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x24
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_add_u32_e32 v4, s6, v0
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v3, s3
; GFX9-NEXT:    ds_cmpst_b64 v4, v[0:1], v[2:3] gds
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    buffer_wbinvl1_vol
; GFX9-NEXT:    s_endpgm
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %gds_ptr = getelementptr i64, ptr addrspace(2) %gds_base, i32 %tid
  %result = cmpxchg ptr addrspace(2) %gds_ptr, i64 %cmp, i64 %new seq_cst seq_cst
  ret void
}

define amdgpu_ps i32 @test_local_p3_s32_uniform(ptr addrspace(3) inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_local_p3_s32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    ds_cmpst_rtn_b32 v0, v0, v1, v2
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(3) %ptr, i32 %cmp, i32 %new seq_cst seq_cst
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i32 @test_local_p3_s32_divergent(ptr addrspace(3) %ptr, i32 %cmp, i32 %new) {
; GFX9-LABEL: test_local_p3_s32_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    ds_cmpst_rtn_b32 v0, v0, v1, v2
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(3) %ptr, i32 %cmp, i32 %new seq_cst seq_cst
  %val = extractvalue { i32, i1 } %result, 0
  ret i32 %val
}

define amdgpu_ps i64 @test_local_p3_s64_uniform(ptr addrspace(3) inreg %ptr, i64 inreg %cmp, i64 inreg %new) {
; GFX9-LABEL: test_local_p3_s64_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_mov_b32 s6, s1
; GFX9-NEXT:    s_mov_b32 s7, s2
; GFX9-NEXT:    s_mov_b32 s2, s3
; GFX9-NEXT:    s_mov_b32 s3, s4
; GFX9-NEXT:    v_mov_b32_e32 v0, s6
; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    v_mov_b32_e32 v4, s0
; GFX9-NEXT:    v_mov_b32_e32 v1, s7
; GFX9-NEXT:    v_mov_b32_e32 v3, s3
; GFX9-NEXT:    ds_cmpst_rtn_b64 v[0:1], v4, v[0:1], v[2:3]
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(3) %ptr, i64 %cmp, i64 %new seq_cst seq_cst
  %val = extractvalue { i64, i1 } %result, 0
  ret i64 %val
}

define amdgpu_ps i64 @test_local_p3_s64_divergent(ptr addrspace(3) %ptr, i64 %cmp, i64 %new) {
; GFX9-LABEL: test_local_p3_s64_divergent:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    ds_cmpst_rtn_b64 v[0:1], v0, v[1:2], v[3:4]
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
; GFX9-NEXT:    ; return to shader part epilog
  %result = cmpxchg ptr addrspace(3) %ptr, i64 %cmp, i64 %new seq_cst seq_cst
  %val = extractvalue { i64, i1 } %result, 0
  ret i64 %val
}

declare i32 @llvm.amdgcn.workitem.id.x()

attributes #0 = { nounwind "amdgpu-gds-size"="4096" }

!0 = !{i32 5, i32 6}