; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck %s

define amdgpu_ps void @readanylane_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: readanylane_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    global_load_dword v1, v0, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    global_store_dword v0, v1, s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile float, ptr addrspace(1) %ptr0
  store float %load, ptr addrspace(1) %ptr1
  ret void
}

define amdgpu_ps float @readanylane_to_physical_vgpr(ptr addrspace(1) inreg %ptr) {
; CHECK-LABEL: readanylane_to_physical_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    global_load_dword v0, v0, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    ; return to shader part epilog
  %load = load volatile float, ptr addrspace(1) %ptr
  ret float %load
}

define amdgpu_ps void @readanylane_to_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: readanylane_to_bitcast_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    global_load_dword v1, v0, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    global_store_dword v0, v1, s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
  %bitcast = bitcast <2 x i16> %load to i32
  store i32 %bitcast, ptr addrspace(1) %ptr1
  ret void
}

define amdgpu_ps float @readanylane_to_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: readanylane_to_bitcast_to_physical_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    global_load_dword v0, v0, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    ; return to shader part epilog
  %load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
  %bitcast = bitcast <2 x i16> %load to float
  ret float %bitcast
}

define amdgpu_ps void @unmerge_readanylane_merge_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: unmerge_readanylane_merge_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile i64, ptr addrspace(1) %ptr0
  store i64 %load, ptr addrspace(1) %ptr1
  ret void
}

;define amdgpu_ps double @unmerge_readanylane_merge_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
;  %load = load volatile double, ptr addrspace(1) %ptr0
;  ret double %load
;}

define amdgpu_ps void @unmerge_readanylane_merge_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: unmerge_readanylane_merge_bitcast_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
  %bitcast = bitcast <2 x i32> %load to double
  store double %bitcast, ptr addrspace(1) %ptr1
  ret void
}

;define amdgpu_ps double @unmerge_readanylane_merge_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
;  %load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
;  %bitcast = bitcast <2 x i32> %load to double
;  ret double %bitcast
;}

define amdgpu_ps void @unmerge_readanylane_merge_extract_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: unmerge_readanylane_merge_extract_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    global_store_dword v2, v1, s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
  %extracted = extractelement <2 x i32> %load, i32 1
  store i32 %extracted, ptr addrspace(1) %ptr1
  ret void
}

define amdgpu_ps float @unmerge_readanylane_merge_extract_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: unmerge_readanylane_merge_extract_to_physical_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, v1
; CHECK-NEXT:    ; return to shader part epilog
  %load = load volatile <2 x float>, ptr addrspace(1) %ptr0
  %extracted = extractelement <2 x float> %load, i32 1
  ret float %extracted
}

define amdgpu_ps void @unmerge_readanylane_merge_extract_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: unmerge_readanylane_merge_extract_bitcast_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    global_store_dword v2, v0, s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile <4 x i16>, ptr addrspace(1) %ptr0
  %extracted = shufflevector <4 x i16> %load, <4 x i16> %load, <2 x i32> <i32 0, i32 1>
  %bitcast = bitcast <2 x i16> %extracted to float
  store float %bitcast, ptr addrspace(1) %ptr1
  ret void
}

define amdgpu_ps float @unmerge_readanylane_merge_extract_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: unmerge_readanylane_merge_extract_bitcast_to_physical_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    ; return to shader part epilog
  %load = load volatile <4 x i16>, ptr addrspace(1) %ptr0
  %extracted = shufflevector <4 x i16> %load, <4 x i16> %load, <2 x i32> <i32 0, i32 1>
  %bitcast = bitcast <2 x i16> %extracted to float
  ret float %bitcast
}

define amdgpu_ps void @op_readanylanes_merge_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: op_readanylanes_merge_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; CHECK-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; CHECK-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile <2 x float>, ptr addrspace(1) %ptr0
  %fneg = fneg <2 x float> %load
  store <2 x float> %fneg, ptr addrspace(1) %ptr1
  ret void
}

define amdgpu_ps void @op_readanylanes_merge_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
; CHECK-LABEL: op_readanylanes_merge_bitcast_to_virtual_vgpr:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
; CHECK-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; CHECK-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
; CHECK-NEXT:    s_endpgm
  %load = load volatile <2 x float>, ptr addrspace(1) %ptr0
  %fneg = fneg <2 x float> %load
  %bitcast = bitcast <2 x float> %fneg to double
  store double %bitcast, ptr addrspace(1) %ptr1
  ret void
}