# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s

# COM: Check that the pass doesn't crash.

---
name: test_inline_asm
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
    dx10-clamp: true
body: |
  bb.1 :
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_inline_asm
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
    ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", attdialect, regdef:VGPR_32, def %5(s32)
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %2:vgpr(s32) = COPY %1(s32)
    %3:vgpr(s32) = G_FMUL %0, %2
    %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
    INLINEASM &"v_mov_b32 $0, 0", attdialect, regdef:VGPR_32, def %5:vgpr_32
    %6:vgpr(s32) = COPY %4(s32)
    %7:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %6(s32)
    $vgpr0 = COPY %7(s32)
...

---
name: test_unmerge_values
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
    dx10-clamp: true
body: |
  bb.1 :
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_unmerge_values
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
    ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], [[C2]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[C2]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %2:vgpr(s32) = COPY %1(s32)
    %3:vgpr(s32) = G_FMUL %0, %2
    %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
    %5:vgpr(s64) = G_CONSTANT i64 123456789
    %6:vgpr(s32), %7:vgpr(s32) = G_UNMERGE_VALUES %5(s64)
    %8:vgpr(s32) = COPY %4(s32)
    %9:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %7(s32), %8(s32)
    $vgpr0 = COPY %7(s32)
...