# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s

---
name: interp_p2_sss
legalized: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-LABEL: name: interp_p2_sss
    ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2), [[COPY3]](s32), [[COPY4]](s32), 1, 1, [[COPY2]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY $sgpr2
    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2), %0, %1, 1, 1, %2
...

---
name: interp_p2_ssv
legalized: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $vgpr0
    ; CHECK-LABEL: name: interp_p2_ssv
    ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY2]](s32)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2), [[COPY3]](s32), [[COPY4]](s32), 1, 1, [[INTRINSIC_CONVERGENT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY  $vgpr0
    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2), %0, %1, 1, 1, %2
...