# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s

---
name: and_s1_sgpr_sgpr
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: and_s1_sgpr_sgpr
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s1) = G_TRUNC %0
    %3:_(s1) = G_TRUNC %1
    %4:_(s1) = G_AND %2, %3
    %5:_(s32) = G_ANYEXT %4
    S_ENDPGM 0, implicit %5
...

---
name: and_s1_scc_scc
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: and_s1_scc_scc
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[ICMP1]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s1) = G_ICMP intpred(eq), %0, %2
    %4:_(s1) = G_ICMP intpred(eq), %1, %2
    %5:_(s1) = G_AND %3, %4
    %6:_(s32) = G_ANYEXT %5
    S_ENDPGM 0, implicit %6
...

---
name: and_s1_vgpr_vgpr
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: and_s1_vgpr_vgpr
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[COPY1]], [[C]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND1]](s32), [[C1]]
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AND2]](s1), [[C]], [[C1]]
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_TRUNC %0
    %3:_(s1) = G_TRUNC %1
    %4:_(s1) = G_AND %2, %3
    %5:_(s32) = G_ANYEXT %4
...

---
name: and_s1_vcc_vcc
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: and_s1_vcc_vcc
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s1) = G_ICMP intpred(eq), %0, %2
    %4:_(s1) = G_ICMP intpred(eq), %1, %2
    %5:_(s1) = G_AND %3, %4
...

---
name: and_s1_sgpr_vgpr
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: and_s1_sgpr_vgpr
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY1]], [[C]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
    ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY]](s32)
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AMDGPU_COPY_VCC_SCC]], [[ICMP]]
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $vgpr0
    %2:_(s1) = G_TRUNC %0
    %3:_(s1) = G_TRUNC %1
    %4:_(s1) = G_AND %2, %3
...

---
name: and_s1_vgpr_sgpr
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr0
    ; CHECK-LABEL: name: and_s1_vgpr_sgpr
    ; CHECK: liveins: $vgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
    ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY1]](s32)
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[AMDGPU_COPY_VCC_SCC]]
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $sgpr0
    %2:_(s1) = G_TRUNC %0
    %3:_(s1) = G_TRUNC %1
    %4:_(s1) = G_AND %2, %3
...

# FIXME: Should just change the result bank of the scc compare.
---
name: and_s1_scc_vcc
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: and_s1_scc_vcc
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]
    ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[AMDGPU_COPY_VCC_SCC]], [[ICMP1]]
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s1) = G_ICMP intpred(eq), %0, %2
    %4:_(s1) = G_ICMP intpred(eq), %1, %2
    %5:_(s1) = G_AND %3, %4
...

---
name: and_s1_vcc_scc
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: and_s1_vcc_scc
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s1) = G_ICMP intpred(eq), %0, %2
    %4:_(s1) = G_ICMP intpred(eq), %1, %2
    %5:_(s1) = G_AND %3, %4
...


# Test with a known result bank
# ---
# name: and_s1_vcc_sgpr_sgpr
# legalized: true

# body: |
#   bb.0:
#     liveins: $sgpr0, $sgpr1

#     %0:_(s32) = COPY $sgpr0
#     %1:_(s32) = COPY $sgpr1
#     %2:_(s1) = G_TRUNC %0
#     %3:_(s1) = G_TRUNC %1
#     %4:vcc(s1) = G_AND %2, %3
# ...

# ---
# name: and_s1_vcc_vgpr_vgpr
# legalized: true

# body: |
#   bb.0:
#     liveins: $vgpr0, $vgpr1

#     %0:_(s32) = COPY $vgpr0
#     %1:_(s32) = COPY $vgpr1
#     %2:_(s1) = G_TRUNC %0
#     %3:_(s1) = G_TRUNC %1
#     %4:vcc(s1) = G_AND %2, %3
# ...

# ---
# name: and_s1_vcc_vgpr_sgpr
# legalized: true

# body: |
#   bb.0:
#     liveins: $vgpr0, $sgpr0
#     %0:_(s32) = COPY $vgpr0
#     %1:_(s32) = COPY $sgpr0
#     %2:_(s1) = G_TRUNC %0
#     %3:_(s1) = G_TRUNC %1
#     %4:vcc(s1) = G_AND %2, %3
# ...

# ---
# name: and_s1_vcc_sgpr_vgpr
# legalized: true

# body: |
#   bb.0:
#     liveins: $vgpr0, $sgpr0
#     %0:_(s32) = COPY $sgpr0
#     %1:_(s32) = COPY $vgpr0
#     %2:_(s1) = G_TRUNC %0
#     %3:_(s1) = G_TRUNC %1
#     %4:vcc(s1) = G_AND %2, %3
# ...

---
name: and_s1_vgpr_sgpr_sgpr
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: and_s1_vgpr_sgpr_sgpr
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY2]], [[C]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[AND1]](s32)
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[AMDGPU_COPY_VCC_SCC]]
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY $vgpr0
    %3:_(s1) = G_TRUNC %0
    %4:_(s1) = G_TRUNC %1
    %5:_(s1) = G_TRUNC %2
    %6:_(s1) = G_AND %3, %4
    %7:_(s1) = G_AND %5, %6
...

---
name: and_s1_sgpr_sgpr_sgpr
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: and_s1_sgpr_sgpr_sgpr
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[AND]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[AND1]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY $sgpr0
    %3:_(s1) = G_TRUNC %0
    %4:_(s1) = G_TRUNC %1
    %5:_(s1) = G_TRUNC %2
    %6:_(s1) = G_AND %3, %4
    %7:_(s1) = G_AND %5, %6
    %8:_(s32) = G_ANYEXT %7
    S_ENDPGM 0, implicit %8
...