# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=instruction-select -mattr=+real-true16 -o - %s | FileCheck -check-prefix=GFX11 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -run-pass=instruction-select -mattr=+real-true16 -o - %s | FileCheck -check-prefix=GFX12 %s

---
name: test_merge_values_s16_into_s32_sgpr
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; GFX11-LABEL: name: test_merge_values_s16_into_s32_sgpr
    ; GFX11: liveins: $sgpr0, $sgpr1
    ; GFX11-NEXT: {{  $}}
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX11-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
    ; GFX11-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
    ;
    ; GFX12-LABEL: name: test_merge_values_s16_into_s32_sgpr
    ; GFX12: liveins: $sgpr0, $sgpr1
    ; GFX12-NEXT: {{  $}}
    ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX12-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
    ; GFX12-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
    %0:sreg_32(s32) = COPY $sgpr0
    %1:sreg_32(s32) = COPY $sgpr1
    %2:sreg_32(s16) = G_TRUNC %0:sreg_32(s32)
    %3:sreg_32(s16) = G_TRUNC %1:sreg_32(s32)
    %4:sreg_32(s32) = G_MERGE_VALUES %2:sreg_32(s16), %3:sreg_32(s16)
    $sgpr0 = COPY %4:sreg_32(s32)
...

---
name: test_build_vector_s16_into_s32_sgpr
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; GFX11-LABEL: name: test_build_vector_s16_into_s32_sgpr
    ; GFX11: liveins: $sgpr0, $sgpr1
    ; GFX11-NEXT: {{  $}}
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX11-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
    ; GFX11-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
    ;
    ; GFX12-LABEL: name: test_build_vector_s16_into_s32_sgpr
    ; GFX12: liveins: $sgpr0, $sgpr1
    ; GFX12-NEXT: {{  $}}
    ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX12-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
    ; GFX12-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
    %0:sreg_32(s32) = COPY $sgpr0
    %1:sreg_32(s32) = COPY $sgpr1
    %2:sreg_32(s16) = G_TRUNC %0:sreg_32(s32)
    %3:sreg_32(s16) = G_TRUNC %1:sreg_32(s32)
    %4:sreg_32(<2 x s16>) = G_BUILD_VECTOR %2:sreg_32(s16), %3:sreg_32(s16)
    $sgpr0 = COPY %4:sreg_32(<2 x s16>)
...

---
name: test_merge_values_s16_into_s32_vgpr
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    ; GFX11-LABEL: name: test_merge_values_s16_into_s32_vgpr
    ; GFX11: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    ; GFX11-NEXT: {{  $}}
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
    ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
    ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
    ; GFX11-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
    ;
    ; GFX12-LABEL: name: test_merge_values_s16_into_s32_vgpr
    ; GFX12: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    ; GFX12-NEXT: {{  $}}
    ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
    ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
    ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
    ; GFX12-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
    %0:vgpr_32(s32) = COPY $vgpr0
    %1:vgpr_32(s32) = COPY $vgpr1
    %2:vgpr_16(s16) = G_TRUNC %0:vgpr_32(s32)
    %3:vgpr_16(s16) = G_TRUNC %1:vgpr_32(s32)
    %4:vgpr_32(s32) = G_MERGE_VALUES %2:vgpr_16(s16), %3:vgpr_16(s16)
    $vgpr0 = COPY %4:vgpr_32(s32)
...

---
name: test_build_vector_s16_into_s32_vgpr
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX11-LABEL: name: test_build_vector_s16_into_s32_vgpr
    ; GFX11: liveins: $vgpr0, $vgpr1
    ; GFX11-NEXT: {{  $}}
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
    ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
    ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
    ; GFX11-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
    ;
    ; GFX12-LABEL: name: test_build_vector_s16_into_s32_vgpr
    ; GFX12: liveins: $vgpr0, $vgpr1
    ; GFX12-NEXT: {{  $}}
    ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
    ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
    ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
    ; GFX12-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
    %0:vgpr_32(s32) = COPY $vgpr0
    %1:vgpr_32(s32) = COPY $vgpr1
    %2:vgpr_16(s16) = G_TRUNC %0:vgpr_32(s32)
    %3:vgpr_16(s16) = G_TRUNC %1:vgpr_32(s32)
    %4:vgpr_32(<2 x s16>) = G_BUILD_VECTOR %2:vgpr_16(s16), %3:vgpr_16(s16)
    $vgpr0 = COPY %4:vgpr_32(<2 x s16>)
...