; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -o - %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+real-true16 -o - %s | FileCheck -check-prefix=GFX12 %s

define amdgpu_ps i48 @test_merge_values_sgpr(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {
; GFX11-LABEL: test_merge_values_sgpr:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_mov_b64 s[0:1], -1
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    s_lshr_b32 s2, s0, 16
; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
; GFX11-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: test_merge_values_sgpr:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_mov_b64 s[0:1], -1
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT:    s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX12-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT:    s_lshr_b32 s2, s0, 16
; GFX12-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
; GFX12-NEXT:    ; return to shader part epilog
  %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>
  %and = and <3 x i16> %src0, %not.src1
  %cast = bitcast <3 x i16> %and to i48
  ret i48 %cast
}

define amdgpu_ps i48 @test_merge_values_vgpr(<3 x i16> %src0, <3 x i16> %src1) {
; GFX11-LABEL: test_merge_values_vgpr:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    v_xor_b32_e32 v2, -1, v2
; GFX11-NEXT:    v_xor_b32_e32 v3, -1, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX11-NEXT:    v_and_b32_e32 v1, v1, v3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
; GFX11-NEXT:    v_readfirstlane_b32 s1, v1
; GFX11-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: test_merge_values_vgpr:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_xor_b32_e32 v2, -1, v2
; GFX12-NEXT:    v_xor_b32_e32 v3, -1, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX12-NEXT:    v_and_b32_e32 v1, v1, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_readfirstlane_b32 s0, v0
; GFX12-NEXT:    v_readfirstlane_b32 s1, v1
; GFX12-NEXT:    ; return to shader part epilog
  %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>
  %and = and <3 x i16> %src0, %not.src1
  %cast = bitcast <3 x i16> %and to i48
  ret i48 %cast
}