; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s ; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -new-reg-bank-select -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s define amdgpu_kernel void @udivrem_i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i32 %x, i32 %y) { ; GFX8-LABEL: udivrem_i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX8-NEXT: s_sub_i32 s0, 0, s5 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s6, v0 ; GFX8-NEXT: s_mul_i32 s0, s0, s6 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s7, v0 ; GFX8-NEXT: s_add_i32 s6, s6, s7 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s5 ; GFX8-NEXT: s_sub_i32 s1, s4, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s6, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s5, s1 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: s_sub_i32 s6, 0, s5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v0 ; GFX9-NEXT: s_mul_i32 s6, s6, s7 ; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6 ; GFX9-NEXT: s_add_i32 s7, s7, s6 ; GFX9-NEXT: s_mul_hi_u32 s6, s4, s7 ; GFX9-NEXT: s_mul_i32 s7, s6, s5 ; GFX9-NEXT: s_sub_i32 s4, s4, s7 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s8, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s8, s4 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s5, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: s_cselect_b32 s4, s5, s4 ; GFX9-NEXT: global_store_dword v1, v0, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: global_store_dword v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX10-NEXT: s_sub_i32 s1, 0, s5 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: s_mul_i32 s1, s1, s0 ; GFX10-NEXT: s_mul_hi_u32 s1, s0, s1 ; GFX10-NEXT: s_add_i32 s0, s0, s1 ; GFX10-NEXT: s_mul_hi_u32 s6, s4, s0 ; GFX10-NEXT: s_mul_i32 s0, s6, s5 ; GFX10-NEXT: s_sub_i32 s4, s4, s0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s4, s5 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s6, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_sub_i32 s8, s4, s5 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s4, s8, s4 ; GFX10-NEXT: s_cmp_ge_u32 s4, s5 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s6, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_sub_i32 s5, s4, s5 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-NEXT: s_cselect_b32 s4, s5, s4 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv i32 %x, %y store i32 %div, ptr addrspace(1) %out0 %rem = urem i32 %x, %y store i32 %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i64 %x, i64 %y) { ; GFX8-LABEL: udivrem_i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX8-NEXT: s_sub_u32 s8, 0, s6 ; GFX8-NEXT: s_subb_u32 s9, 0, s7 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_hi_u32 v2, s8, v0 ; GFX8-NEXT: v_readfirstlane_b32 s12, v0 ; GFX8-NEXT: s_mul_i32 s13, s8, s12 ; GFX8-NEXT: v_readfirstlane_b32 s10, v1 ; GFX8-NEXT: v_mul_hi_u32 v3, v0, s13 ; GFX8-NEXT: s_mul_i32 s11, s8, s10 ; GFX8-NEXT: s_mul_i32 s15, s10, s13 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, s13 ; GFX8-NEXT: v_readfirstlane_b32 s13, v2 ; GFX8-NEXT: s_mul_i32 s14, s9, s12 ; GFX8-NEXT: s_add_u32 s11, s11, s13 ; GFX8-NEXT: s_add_u32 s11, s14, s11 ; GFX8-NEXT: v_readfirstlane_b32 s13, v3 ; GFX8-NEXT: s_mul_i32 s16, s12, s11 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s11 ; GFX8-NEXT: s_add_u32 s13, s13, s16 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_add_u32 s13, s13, s15 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: v_readfirstlane_b32 s14, v4 ; GFX8-NEXT: s_add_i32 s16, s16, s13 ; GFX8-NEXT: v_readfirstlane_b32 s13, v0 ; GFX8-NEXT: s_mul_i32 s15, s10, s11 ; GFX8-NEXT: s_add_u32 s13, s14, s13 ; GFX8-NEXT: s_cselect_b32 s14, 1, 0 ; GFX8-NEXT: s_add_u32 s13, s13, s15 ; GFX8-NEXT: s_cselect_b32 s15, 1, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s11 ; GFX8-NEXT: s_add_i32 s14, s14, s15 ; GFX8-NEXT: s_add_u32 s11, s13, s16 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_add_i32 s14, s14, s13 ; GFX8-NEXT: v_readfirstlane_b32 s13, v0 ; GFX8-NEXT: s_add_i32 s13, s13, s14 ; GFX8-NEXT: s_add_u32 s11, s12, s11 ; GFX8-NEXT: v_mov_b32_e32 v0, s11 ; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX8-NEXT: s_mul_i32 s12, s8, s11 ; GFX8-NEXT: s_addc_u32 s10, s10, s13 ; GFX8-NEXT: s_mul_i32 s8, s8, s10 ; GFX8-NEXT: v_readfirstlane_b32 s13, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s12 ; GFX8-NEXT: v_mul_hi_u32 v1, s11, v0 ; GFX8-NEXT: s_add_u32 s8, s8, s13 ; GFX8-NEXT: s_mul_i32 s9, s9, s11 ; GFX8-NEXT: s_add_u32 s8, s9, s8 ; GFX8-NEXT: v_readfirstlane_b32 s9, v1 ; GFX8-NEXT: v_mov_b32_e32 v1, s8 ; GFX8-NEXT: s_mul_i32 s13, s11, s8 ; GFX8-NEXT: v_mul_hi_u32 v0, s10, v0 ; GFX8-NEXT: v_mul_hi_u32 v2, s11, v1 ; GFX8-NEXT: s_mul_i32 s12, s10, s12 ; GFX8-NEXT: s_add_u32 s9, s9, s13 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_add_u32 s9, s9, s12 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s13, s13, s9 ; GFX8-NEXT: v_readfirstlane_b32 s9, v0 ; GFX8-NEXT: v_readfirstlane_b32 s12, v2 ; GFX8-NEXT: s_mul_i32 s8, s10, s8 ; GFX8-NEXT: s_add_u32 s9, s9, s12 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_add_u32 s8, s9, s8 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, s10, v1 ; GFX8-NEXT: s_add_i32 s9, s12, s9 ; GFX8-NEXT: s_add_u32 s8, s8, s13 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_add_i32 s9, s9, s12 ; GFX8-NEXT: v_readfirstlane_b32 s12, v0 ; GFX8-NEXT: s_add_i32 s12, s12, s9 ; GFX8-NEXT: s_add_u32 s8, s11, s8 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX8-NEXT: s_addc_u32 s9, s10, s12 ; GFX8-NEXT: v_mov_b32_e32 v1, s9 ; GFX8-NEXT: s_mul_i32 s11, s4, s9 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s5 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s8 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v1 ; GFX8-NEXT: s_mul_i32 s12, s5, s8 ; GFX8-NEXT: s_add_u32 s10, s10, s11 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_u32 s10, s10, s12 ; GFX8-NEXT: s_cselect_b32 s8, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s11, s8 ; GFX8-NEXT: v_readfirstlane_b32 s8, v0 ; GFX8-NEXT: v_readfirstlane_b32 s10, v2 ; GFX8-NEXT: s_mul_i32 s9, s5, s9 ; GFX8-NEXT: s_add_u32 s8, s8, s10 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_u32 s8, s8, s9 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s9, s10, s9 ; GFX8-NEXT: s_add_u32 s8, s8, s11 ; GFX8-NEXT: v_mul_hi_u32 v0, s5, v1 ; GFX8-NEXT: v_mov_b32_e32 v1, s8 ; GFX8-NEXT: v_mul_hi_u32 v1, s6, v1 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_i32 s9, s9, s10 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: s_add_i32 s9, s10, s9 ; GFX8-NEXT: v_readfirstlane_b32 s11, v1 ; GFX8-NEXT: s_mul_i32 s12, s6, s9 ; GFX8-NEXT: s_add_u32 s11, s12, s11 ; GFX8-NEXT: s_mul_i32 s12, s7, s8 ; GFX8-NEXT: s_mul_i32 s10, s6, s8 ; GFX8-NEXT: s_add_u32 s12, s12, s11 ; GFX8-NEXT: s_sub_u32 s10, s4, s10 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_subb_u32 s11, s5, s12 ; GFX8-NEXT: s_sub_i32 s5, s5, s12 ; GFX8-NEXT: s_cmp_ge_u32 s11, s7 ; GFX8-NEXT: s_cselect_b32 s4, -1, 0 ; GFX8-NEXT: s_cmp_ge_u32 s10, s6 ; GFX8-NEXT: s_cselect_b32 s12, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s11, s7 ; GFX8-NEXT: s_cselect_b32 s16, s12, s4 ; GFX8-NEXT: s_sub_u32 s4, s10, s6 ; GFX8-NEXT: s_cselect_b32 s17, 1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s13, 0 ; GFX8-NEXT: s_subb_u32 s18, s5, s7 ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 ; GFX8-NEXT: s_subb_u32 s5, s18, 0 ; GFX8-NEXT: s_add_u32 s12, s8, 1 ; GFX8-NEXT: s_addc_u32 s13, s9, 0 ; GFX8-NEXT: s_cmp_ge_u32 s5, s7 ; GFX8-NEXT: s_cselect_b32 s14, -1, 0 ; GFX8-NEXT: s_cmp_ge_u32 s4, s6 ; GFX8-NEXT: s_cselect_b32 s15, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s5, s7 ; GFX8-NEXT: s_cselect_b32 s19, s15, s14 ; GFX8-NEXT: s_add_u32 s14, s12, 1 ; GFX8-NEXT: s_addc_u32 s15, s13, 0 ; GFX8-NEXT: s_sub_u32 s6, s4, s6 ; GFX8-NEXT: s_cselect_b32 s20, 1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 ; GFX8-NEXT: s_subb_u32 s7, s18, s7 ; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: s_subb_u32 s7, s7, 0 ; GFX8-NEXT: s_cmp_lg_u32 s19, 0 ; GFX8-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] ; GFX8-NEXT: s_cmp_lg_u32 s19, 0 ; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11] ; GFX8-NEXT: v_mov_b32_e32 v1, s9 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX9-NEXT: s_sub_u32 s8, 0, s6 ; GFX9-NEXT: s_subb_u32 s9, 0, s7 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_readfirstlane_b32 s10, v1 ; GFX9-NEXT: v_readfirstlane_b32 s12, v0 ; GFX9-NEXT: s_mul_i32 s11, s8, s10 ; GFX9-NEXT: s_mul_hi_u32 s14, s8, s12 ; GFX9-NEXT: s_mul_i32 s15, s9, s12 ; GFX9-NEXT: s_add_u32 s11, s11, s14 ; GFX9-NEXT: s_mul_i32 s13, s8, s12 ; GFX9-NEXT: s_add_u32 s11, s15, s11 ; GFX9-NEXT: s_mul_hi_u32 s14, s12, s13 ; GFX9-NEXT: s_mul_i32 s15, s12, s11 ; GFX9-NEXT: s_mul_i32 s16, s10, s13 ; GFX9-NEXT: s_add_u32 s14, s14, s15 ; GFX9-NEXT: s_cselect_b32 s15, 1, 0 ; GFX9-NEXT: s_add_u32 s14, s14, s16 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_mul_hi_u32 s13, s10, s13 ; GFX9-NEXT: s_mul_hi_u32 s17, s12, s11 ; GFX9-NEXT: s_add_i32 s15, s15, s14 ; GFX9-NEXT: s_mul_i32 s14, s10, s11 ; GFX9-NEXT: s_add_u32 s13, s13, s17 ; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_add_u32 s13, s13, s14 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_add_i32 s14, s16, s14 ; GFX9-NEXT: s_add_u32 s13, s13, s15 ; GFX9-NEXT: s_cselect_b32 s15, 1, 0 ; GFX9-NEXT: s_add_i32 s14, s14, s15 ; GFX9-NEXT: s_mul_hi_u32 s11, s10, s11 ; GFX9-NEXT: s_add_i32 s11, s11, s14 ; GFX9-NEXT: s_add_u32 s12, s12, s13 ; GFX9-NEXT: s_addc_u32 s10, s10, s11 ; GFX9-NEXT: s_mul_i32 s11, s8, s12 ; GFX9-NEXT: s_mul_hi_u32 s13, s8, s12 ; GFX9-NEXT: s_mul_i32 s8, s8, s10 ; GFX9-NEXT: s_add_u32 s8, s8, s13 ; GFX9-NEXT: s_mul_i32 s9, s9, s12 ; GFX9-NEXT: s_add_u32 s8, s9, s8 ; GFX9-NEXT: s_mul_hi_u32 s9, s12, s11 ; GFX9-NEXT: s_mul_i32 s13, s12, s8 ; GFX9-NEXT: s_mul_i32 s14, s10, s11 ; GFX9-NEXT: s_add_u32 s9, s9, s13 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_u32 s9, s9, s14 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s13, s13, s9 ; GFX9-NEXT: s_mul_hi_u32 s9, s10, s11 ; GFX9-NEXT: s_mul_hi_u32 s11, s12, s8 ; GFX9-NEXT: s_mul_i32 s14, s10, s8 ; GFX9-NEXT: s_add_u32 s9, s9, s11 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_u32 s9, s9, s14 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s11, s14 ; GFX9-NEXT: s_add_u32 s9, s9, s13 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s11, s13 ; GFX9-NEXT: s_mul_hi_u32 s8, s10, s8 ; GFX9-NEXT: s_add_i32 s8, s8, s11 ; GFX9-NEXT: s_add_u32 s9, s12, s9 ; GFX9-NEXT: s_addc_u32 s10, s10, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s4, s9 ; GFX9-NEXT: s_mul_i32 s11, s4, s10 ; GFX9-NEXT: s_mul_i32 s12, s5, s9 ; GFX9-NEXT: s_add_u32 s8, s8, s11 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_u32 s8, s8, s12 ; GFX9-NEXT: s_cselect_b32 s8, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s11, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s5, s9 ; GFX9-NEXT: s_mul_hi_u32 s9, s4, s10 ; GFX9-NEXT: s_mul_i32 s12, s5, s10 ; GFX9-NEXT: s_add_u32 s8, s8, s9 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_u32 s8, s8, s12 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: s_add_i32 s9, s9, s12 ; GFX9-NEXT: s_add_u32 s8, s8, s11 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_i32 s9, s9, s11 ; GFX9-NEXT: s_mul_hi_u32 s10, s5, s10 ; GFX9-NEXT: s_add_i32 s9, s10, s9 ; GFX9-NEXT: s_mul_hi_u32 s11, s6, s8 ; GFX9-NEXT: s_mul_i32 s12, s6, s9 ; GFX9-NEXT: s_add_u32 s11, s12, s11 ; GFX9-NEXT: s_mul_i32 s12, s7, s8 ; GFX9-NEXT: s_mul_i32 s10, s6, s8 ; GFX9-NEXT: s_add_u32 s12, s12, s11 ; GFX9-NEXT: s_sub_u32 s10, s4, s10 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_subb_u32 s11, s5, s12 ; GFX9-NEXT: s_sub_i32 s5, s5, s12 ; GFX9-NEXT: s_cmp_ge_u32 s11, s7 ; GFX9-NEXT: s_cselect_b32 s4, -1, 0 ; GFX9-NEXT: s_cmp_ge_u32 s10, s6 ; GFX9-NEXT: s_cselect_b32 s12, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s11, s7 ; GFX9-NEXT: s_cselect_b32 s16, s12, s4 ; GFX9-NEXT: s_sub_u32 s4, s10, s6 ; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_subb_u32 s18, s5, s7 ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 ; GFX9-NEXT: s_subb_u32 s5, s18, 0 ; GFX9-NEXT: s_add_u32 s12, s8, 1 ; GFX9-NEXT: s_addc_u32 s13, s9, 0 ; GFX9-NEXT: s_cmp_ge_u32 s5, s7 ; GFX9-NEXT: s_cselect_b32 s14, -1, 0 ; GFX9-NEXT: s_cmp_ge_u32 s4, s6 ; GFX9-NEXT: s_cselect_b32 s15, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s5, s7 ; GFX9-NEXT: s_cselect_b32 s19, s15, s14 ; GFX9-NEXT: s_add_u32 s14, s12, 1 ; GFX9-NEXT: s_addc_u32 s15, s13, 0 ; GFX9-NEXT: s_sub_u32 s6, s4, s6 ; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 ; GFX9-NEXT: s_subb_u32 s7, s18, s7 ; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_subb_u32 s7, s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s19, 0 ; GFX9-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] ; GFX9-NEXT: s_cmp_lg_u32 s19, 0 ; GFX9-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s8 ; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11] ; GFX9-NEXT: v_mov_b32_e32 v1, s9 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX10-NEXT: s_sub_u32 s10, 0, s6 ; GFX10-NEXT: s_subb_u32 s11, 0, s7 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s8, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_mul_i32 s12, s10, s8 ; GFX10-NEXT: v_readfirstlane_b32 s9, v0 ; GFX10-NEXT: s_mul_hi_u32 s14, s10, s9 ; GFX10-NEXT: s_mul_i32 s15, s11, s9 ; GFX10-NEXT: s_add_i32 s12, s14, s12 ; GFX10-NEXT: s_mul_i32 s13, s10, s9 ; GFX10-NEXT: s_add_i32 s12, s12, s15 ; GFX10-NEXT: s_mul_hi_u32 s14, s9, s13 ; GFX10-NEXT: s_mul_i32 s15, s9, s12 ; GFX10-NEXT: s_mul_i32 s16, s8, s13 ; GFX10-NEXT: s_add_u32 s14, s14, s15 ; GFX10-NEXT: s_cselect_b32 s15, 1, 0 ; GFX10-NEXT: s_add_u32 s14, s14, s16 ; GFX10-NEXT: s_cselect_b32 s14, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s13, s8, s13 ; GFX10-NEXT: s_mul_hi_u32 s17, s9, s12 ; GFX10-NEXT: s_add_i32 s15, s15, s14 ; GFX10-NEXT: s_mul_i32 s16, s8, s12 ; GFX10-NEXT: s_add_u32 s13, s13, s17 ; GFX10-NEXT: s_cselect_b32 s14, 1, 0 ; GFX10-NEXT: s_add_u32 s13, s13, s16 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s12, s8, s12 ; GFX10-NEXT: s_add_i32 s14, s14, s16 ; GFX10-NEXT: s_add_u32 s13, s13, s15 ; GFX10-NEXT: s_cselect_b32 s15, 1, 0 ; GFX10-NEXT: s_add_i32 s14, s14, s15 ; GFX10-NEXT: s_add_i32 s12, s12, s14 ; GFX10-NEXT: s_add_u32 s9, s9, s13 ; GFX10-NEXT: s_addc_u32 s8, s8, s12 ; GFX10-NEXT: s_mul_i32 s12, s10, s9 ; GFX10-NEXT: s_mul_hi_u32 s13, s10, s9 ; GFX10-NEXT: s_mul_i32 s10, s10, s8 ; GFX10-NEXT: s_mul_i32 s11, s11, s9 ; GFX10-NEXT: s_add_i32 s10, s13, s10 ; GFX10-NEXT: s_mul_hi_u32 s14, s9, s12 ; GFX10-NEXT: s_add_i32 s10, s10, s11 ; GFX10-NEXT: s_mul_i32 s13, s8, s12 ; GFX10-NEXT: s_mul_hi_u32 s11, s8, s12 ; GFX10-NEXT: s_mul_i32 s12, s9, s10 ; GFX10-NEXT: s_mul_hi_u32 s15, s9, s10 ; GFX10-NEXT: s_add_u32 s12, s14, s12 ; GFX10-NEXT: s_cselect_b32 s14, 1, 0 ; GFX10-NEXT: s_add_u32 s12, s12, s13 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_mul_i32 s13, s8, s10 ; GFX10-NEXT: s_add_i32 s14, s14, s12 ; GFX10-NEXT: s_add_u32 s11, s11, s15 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_add_u32 s11, s11, s13 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s10, s8, s10 ; GFX10-NEXT: s_add_i32 s12, s12, s13 ; GFX10-NEXT: s_add_u32 s11, s11, s14 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10-NEXT: s_add_i32 s12, s12, s13 ; GFX10-NEXT: s_add_i32 s10, s10, s12 ; GFX10-NEXT: s_add_u32 s9, s9, s11 ; GFX10-NEXT: s_addc_u32 s10, s8, s10 ; GFX10-NEXT: s_mul_hi_u32 s8, s4, s9 ; GFX10-NEXT: s_mul_i32 s12, s4, s10 ; GFX10-NEXT: s_mul_i32 s11, s5, s9 ; GFX10-NEXT: s_add_u32 s8, s8, s12 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_add_u32 s8, s8, s11 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s9, s5, s9 ; GFX10-NEXT: s_mul_hi_u32 s13, s4, s10 ; GFX10-NEXT: s_add_i32 s12, s12, s8 ; GFX10-NEXT: s_mul_i32 s11, s5, s10 ; GFX10-NEXT: s_add_u32 s8, s9, s13 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: s_add_u32 s8, s8, s11 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s10, s5, s10 ; GFX10-NEXT: s_add_i32 s9, s9, s11 ; GFX10-NEXT: s_add_u32 s8, s8, s12 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_mul_i32 s12, s7, s8 ; GFX10-NEXT: s_add_i32 s9, s9, s11 ; GFX10-NEXT: s_add_i32 s9, s10, s9 ; GFX10-NEXT: s_mul_hi_u32 s10, s6, s8 ; GFX10-NEXT: s_mul_i32 s11, s6, s9 ; GFX10-NEXT: s_add_i32 s10, s10, s11 ; GFX10-NEXT: s_mul_i32 s11, s6, s8 ; GFX10-NEXT: s_add_i32 s12, s10, s12 ; GFX10-NEXT: s_sub_u32 s10, s4, s11 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10-NEXT: s_subb_u32 s11, s5, s12 ; GFX10-NEXT: s_sub_i32 s5, s5, s12 ; GFX10-NEXT: s_cmp_ge_u32 s11, s7 ; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: s_cmp_ge_u32 s10, s6 ; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s11, s7 ; GFX10-NEXT: s_cselect_b32 s16, s12, s4 ; GFX10-NEXT: s_sub_u32 s4, s10, s6 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_subb_u32 s18, s5, s7 ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: s_subb_u32 s5, s18, 0 ; GFX10-NEXT: s_add_u32 s12, s8, 1 ; GFX10-NEXT: s_addc_u32 s13, s9, 0 ; GFX10-NEXT: s_cmp_ge_u32 s5, s7 ; GFX10-NEXT: s_cselect_b32 s14, -1, 0 ; GFX10-NEXT: s_cmp_ge_u32 s4, s6 ; GFX10-NEXT: s_cselect_b32 s15, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s5, s7 ; GFX10-NEXT: s_cselect_b32 s19, s15, s14 ; GFX10-NEXT: s_add_u32 s14, s12, 1 ; GFX10-NEXT: s_addc_u32 s15, s13, 0 ; GFX10-NEXT: s_sub_u32 s6, s4, s6 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: s_subb_u32 s7, s18, s7 ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_subb_u32 s7, s7, 0 ; GFX10-NEXT: s_cmp_lg_u32 s19, 0 ; GFX10-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] ; GFX10-NEXT: s_cmp_lg_u32 s19, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11] ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv i64 %x, %y store i64 %div, ptr addrspace(1) %out0 %rem = urem i64 %x, %y store i64 %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i32> %x, <2 x i32> %y) { ; GFX8-LABEL: udivrem_v2i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX8-NEXT: s_sub_i32 s8, 0, s6 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s9, v0 ; GFX8-NEXT: s_mul_i32 s8, s8, s9 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s8 ; GFX8-NEXT: v_readfirstlane_b32 s8, v0 ; GFX8-NEXT: s_add_i32 s8, s9, s8 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s8, v1 ; GFX8-NEXT: v_readfirstlane_b32 s9, v0 ; GFX8-NEXT: s_mul_i32 s10, s9, s6 ; GFX8-NEXT: s_sub_i32 s4, s4, s10 ; GFX8-NEXT: s_cmp_ge_u32 s4, s6 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_cselect_b32 s9, s11, s9 ; GFX8-NEXT: s_sub_i32 s11, s4, s6 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_cselect_b32 s10, s11, s4 ; GFX8-NEXT: s_cmp_ge_u32 s10, s6 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_i32 s4, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cselect_b32 s4, s4, s9 ; GFX8-NEXT: s_sub_i32 s6, s10, s6 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cselect_b32 s6, s6, s10 ; GFX8-NEXT: s_sub_i32 s9, 0, s7 ; GFX8-NEXT: s_mul_i32 s9, s9, s8 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s9 ; GFX8-NEXT: v_readfirstlane_b32 s9, v0 ; GFX8-NEXT: s_add_i32 s8, s8, s9 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: v_mul_hi_u32 v2, s5, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s7 ; GFX8-NEXT: s_sub_i32 s1, s5, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s7 ; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_add_i32 s8, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_cselect_b32 s0, s8, s0 ; GFX8-NEXT: s_sub_i32 s8, s1, s7 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_cselect_b32 s1, s8, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s7 ; GFX8-NEXT: s_cselect_b32 s8, 1, 0 ; GFX8-NEXT: s_add_i32 s5, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: s_cselect_b32 s5, s5, s0 ; GFX8-NEXT: s_sub_i32 s0, s1, s7 ; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v3, s5 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: s_cselect_b32 s7, s0, s1 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_v2i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX9-NEXT: s_sub_i32 s8, 0, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s9, v0 ; GFX9-NEXT: s_mul_i32 s8, s8, s9 ; GFX9-NEXT: s_mul_hi_u32 s8, s9, s8 ; GFX9-NEXT: s_add_i32 s9, s9, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s4, s9 ; GFX9-NEXT: s_mul_i32 s9, s8, s6 ; GFX9-NEXT: s_sub_i32 s4, s4, s9 ; GFX9-NEXT: s_cmp_ge_u32 s4, s6 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s8, s11, s8 ; GFX9-NEXT: s_sub_i32 s11, s4, s6 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s9, s11, s4 ; GFX9-NEXT: s_cmp_ge_u32 s9, s6 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_i32 s4, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 ; GFX9-NEXT: s_cselect_b32 s4, s4, s8 ; GFX9-NEXT: s_sub_i32 s6, s9, s6 ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 ; GFX9-NEXT: v_readfirstlane_b32 s10, v1 ; GFX9-NEXT: s_cselect_b32 s6, s6, s9 ; GFX9-NEXT: s_sub_i32 s8, 0, s7 ; GFX9-NEXT: s_mul_i32 s8, s8, s10 ; GFX9-NEXT: s_mul_hi_u32 s8, s10, s8 ; GFX9-NEXT: s_add_i32 s10, s10, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s5, s10 ; GFX9-NEXT: s_mul_i32 s9, s8, s7 ; GFX9-NEXT: s_sub_i32 s5, s5, s9 ; GFX9-NEXT: s_cmp_ge_u32 s5, s7 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s8, s10, s8 ; GFX9-NEXT: s_sub_i32 s10, s5, s7 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s9, s10, s5 ; GFX9-NEXT: s_cmp_ge_u32 s9, s7 ; GFX9-NEXT: s_cselect_b32 s10, 1, 0 ; GFX9-NEXT: s_add_i32 s5, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s10, 0 ; GFX9-NEXT: s_cselect_b32 s5, s5, s8 ; GFX9-NEXT: s_sub_i32 s7, s9, s7 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: s_cmp_lg_u32 s10, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: s_cselect_b32 s7, s7, s9 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_v2i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX10-NEXT: s_sub_i32 s9, 0, s6 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s8, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v1 ; GFX10-NEXT: s_mul_i32 s9, s9, s8 ; GFX10-NEXT: s_mul_hi_u32 s9, s8, s9 ; GFX10-NEXT: s_add_i32 s8, s8, s9 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: s_mul_hi_u32 s8, s4, s8 ; GFX10-NEXT: s_mul_i32 s9, s8, s6 ; GFX10-NEXT: s_sub_i32 s4, s4, s9 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cmp_ge_u32 s4, s6 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: s_add_i32 s10, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: v_readfirstlane_b32 s11, v0 ; GFX10-NEXT: s_cselect_b32 s8, s10, s8 ; GFX10-NEXT: s_sub_i32 s10, s4, s6 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_cselect_b32 s9, s10, s4 ; GFX10-NEXT: s_cmp_ge_u32 s9, s6 ; GFX10-NEXT: s_cselect_b32 s10, 1, 0 ; GFX10-NEXT: s_add_i32 s4, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: s_cselect_b32 s4, s4, s8 ; GFX10-NEXT: s_sub_i32 s6, s9, s6 ; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: s_cselect_b32 s6, s6, s9 ; GFX10-NEXT: s_sub_i32 s8, 0, s7 ; GFX10-NEXT: s_mul_i32 s8, s8, s11 ; GFX10-NEXT: s_mul_hi_u32 s8, s11, s8 ; GFX10-NEXT: s_add_i32 s11, s11, s8 ; GFX10-NEXT: s_mul_hi_u32 s8, s5, s11 ; GFX10-NEXT: s_mul_i32 s9, s8, s7 ; GFX10-NEXT: s_sub_i32 s5, s5, s9 ; GFX10-NEXT: s_cmp_ge_u32 s5, s7 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: s_add_i32 s10, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_cselect_b32 s8, s10, s8 ; GFX10-NEXT: s_sub_i32 s10, s5, s7 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_cselect_b32 s9, s10, s5 ; GFX10-NEXT: s_cmp_ge_u32 s9, s7 ; GFX10-NEXT: s_cselect_b32 s10, 1, 0 ; GFX10-NEXT: s_add_i32 s5, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: s_cselect_b32 s5, s5, s8 ; GFX10-NEXT: s_sub_i32 s7, s9, s7 ; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: s_cselect_b32 s7, s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s7 ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv <2 x i32> %x, %y store <2 x i32> %div, ptr addrspace(1) %out0 %rem = urem <2 x i32> %x, %y store <2 x i32> %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <4 x i32> %x, <4 x i32> %y) { ; GFX8-LABEL: udivrem_v4i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX8-NEXT: s_sub_i32 s10, 0, s4 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s6 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; GFX8-NEXT: v_readfirstlane_b32 s11, v0 ; GFX8-NEXT: s_mul_i32 s10, s10, s11 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s10 ; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: s_add_i32 s10, s11, s10 ; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s10, v1 ; GFX8-NEXT: v_readfirstlane_b32 s11, v0 ; GFX8-NEXT: s_mul_i32 s12, s11, s4 ; GFX8-NEXT: s_sub_i32 s0, s0, s12 ; GFX8-NEXT: s_cmp_ge_u32 s0, s4 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_add_i32 s13, s11, 1 ; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cselect_b32 s11, s13, s11 ; GFX8-NEXT: s_sub_i32 s13, s0, s4 ; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cselect_b32 s0, s13, s0 ; GFX8-NEXT: s_cmp_ge_u32 s0, s4 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_add_i32 s12, s11, 1 ; GFX8-NEXT: s_cmp_lg_u32 s13, 0 ; GFX8-NEXT: s_cselect_b32 s12, s12, s11 ; GFX8-NEXT: s_sub_i32 s4, s0, s4 ; GFX8-NEXT: s_cmp_lg_u32 s13, 0 ; GFX8-NEXT: s_cselect_b32 s0, s4, s0 ; GFX8-NEXT: s_sub_i32 s4, 0, s5 ; GFX8-NEXT: s_mul_i32 s4, s4, s10 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s4 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: s_add_i32 s4, s10, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v2 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: s_mul_i32 s11, s10, s5 ; GFX8-NEXT: s_sub_i32 s1, s1, s11 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_i32 s13, s10, 1 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cselect_b32 s10, s13, s10 ; GFX8-NEXT: s_sub_i32 s13, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cselect_b32 s1, s13, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_i32 s13, s10, 1 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cselect_b32 s13, s13, s10 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cselect_b32 s1, s5, s1 ; GFX8-NEXT: s_sub_i32 s5, 0, s6 ; GFX8-NEXT: s_mul_i32 s5, s5, s4 ; GFX8-NEXT: v_mul_hi_u32 v0, v2, s5 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v0 ; GFX8-NEXT: s_add_i32 s4, s4, s5 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v0 ; GFX8-NEXT: s_mul_i32 s10, s5, s6 ; GFX8-NEXT: s_sub_i32 s2, s2, s10 ; GFX8-NEXT: s_cmp_ge_u32 s2, s6 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_cselect_b32 s5, s11, s5 ; GFX8-NEXT: s_sub_i32 s11, s2, s6 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_cselect_b32 s2, s11, s2 ; GFX8-NEXT: s_cmp_ge_u32 s2, s6 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_cselect_b32 s14, s11, s5 ; GFX8-NEXT: s_sub_i32 s5, s2, s6 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_cselect_b32 s2, s5, s2 ; GFX8-NEXT: s_sub_i32 s5, 0, s7 ; GFX8-NEXT: s_mul_i32 s5, s5, s4 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s5 ; GFX8-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s5, v0 ; GFX8-NEXT: s_add_i32 s4, s4, s5 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v4, s8 ; GFX8-NEXT: v_mov_b32_e32 v5, s9 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: s_mul_i32 s5, s4, s7 ; GFX8-NEXT: s_sub_i32 s3, s3, s5 ; GFX8-NEXT: s_cmp_ge_u32 s3, s7 ; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s4, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_cselect_b32 s4, s6, s4 ; GFX8-NEXT: s_sub_i32 s6, s3, s7 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_cselect_b32 s3, s6, s3 ; GFX8-NEXT: s_cmp_ge_u32 s3, s7 ; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s4, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_cselect_b32 s15, s6, s4 ; GFX8-NEXT: s_sub_i32 s4, s3, s7 ; GFX8-NEXT: v_mov_b32_e32 v0, s12 ; GFX8-NEXT: v_mov_b32_e32 v1, s13 ; GFX8-NEXT: v_mov_b32_e32 v2, s14 ; GFX8-NEXT: v_mov_b32_e32 v3, s15 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_cselect_b32 s3, s4, s3 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NEXT: v_mov_b32_e32 v4, s10 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v5, s11 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_v4i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10 ; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX9-NEXT: s_sub_i32 s12, 0, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s13, v0 ; GFX9-NEXT: s_mul_i32 s12, s12, s13 ; GFX9-NEXT: s_mul_hi_u32 s12, s13, s12 ; GFX9-NEXT: s_add_i32 s13, s13, s12 ; GFX9-NEXT: s_mul_hi_u32 s12, s0, s13 ; GFX9-NEXT: s_mul_i32 s13, s12, s4 ; GFX9-NEXT: s_sub_i32 s0, s0, s13 ; GFX9-NEXT: s_cmp_ge_u32 s0, s4 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s15, s12, 1 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cselect_b32 s12, s15, s12 ; GFX9-NEXT: s_sub_i32 s15, s0, s4 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cselect_b32 s13, s15, s0 ; GFX9-NEXT: s_cmp_ge_u32 s13, s4 ; GFX9-NEXT: s_cselect_b32 s15, 1, 0 ; GFX9-NEXT: s_add_i32 s0, s12, 1 ; GFX9-NEXT: s_cmp_lg_u32 s15, 0 ; GFX9-NEXT: s_cselect_b32 s0, s0, s12 ; GFX9-NEXT: s_sub_i32 s4, s13, s4 ; GFX9-NEXT: s_cmp_lg_u32 s15, 0 ; GFX9-NEXT: v_readfirstlane_b32 s14, v1 ; GFX9-NEXT: s_cselect_b32 s4, s4, s13 ; GFX9-NEXT: s_sub_i32 s12, 0, s5 ; GFX9-NEXT: s_mul_i32 s12, s12, s14 ; GFX9-NEXT: s_mul_hi_u32 s12, s14, s12 ; GFX9-NEXT: s_add_i32 s14, s14, s12 ; GFX9-NEXT: s_mul_hi_u32 s12, s1, s14 ; GFX9-NEXT: s_mul_i32 s13, s12, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX9-NEXT: s_sub_i32 s1, s1, s13 ; GFX9-NEXT: s_cmp_ge_u32 s1, s5 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s14, s12, 1 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_cselect_b32 s12, s14, s12 ; GFX9-NEXT: s_sub_i32 s14, s1, s5 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cselect_b32 s13, s14, s1 ; GFX9-NEXT: s_cmp_ge_u32 s13, s5 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_add_i32 s1, s12, 1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: s_cselect_b32 s1, s1, s12 ; GFX9-NEXT: s_sub_i32 s5, s13, s5 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: s_cselect_b32 s5, s5, s13 ; GFX9-NEXT: v_readfirstlane_b32 s12, v0 ; GFX9-NEXT: s_sub_i32 s13, 0, s6 ; GFX9-NEXT: s_mul_i32 s13, s13, s12 ; GFX9-NEXT: s_mul_hi_u32 s13, s12, s13 ; GFX9-NEXT: s_add_i32 s12, s12, s13 ; GFX9-NEXT: s_mul_hi_u32 s12, s2, s12 ; GFX9-NEXT: s_mul_i32 s13, s12, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX9-NEXT: s_sub_i32 s2, s2, s13 ; GFX9-NEXT: s_cmp_ge_u32 s2, s6 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s14, s12, 1 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_cselect_b32 s12, s14, s12 ; GFX9-NEXT: s_sub_i32 s14, s2, s6 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cselect_b32 s13, s14, s2 ; GFX9-NEXT: s_cmp_ge_u32 s13, s6 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_add_i32 s2, s12, 1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: s_cselect_b32 s2, s2, s12 ; GFX9-NEXT: s_sub_i32 s6, s13, s6 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: s_cselect_b32 s6, s6, s13 ; GFX9-NEXT: v_readfirstlane_b32 s12, v0 ; GFX9-NEXT: s_sub_i32 s13, 0, s7 ; GFX9-NEXT: s_mul_i32 s13, s13, s12 ; GFX9-NEXT: s_mul_hi_u32 s13, s12, s13 ; GFX9-NEXT: s_add_i32 s12, s12, s13 ; GFX9-NEXT: s_mul_hi_u32 s12, s3, s12 ; GFX9-NEXT: s_mul_i32 s13, s12, s7 ; GFX9-NEXT: s_sub_i32 s3, s3, s13 ; GFX9-NEXT: s_cmp_ge_u32 s3, s7 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s14, s12, 1 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cselect_b32 s12, s14, s12 ; GFX9-NEXT: s_sub_i32 s14, s3, s7 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cselect_b32 s13, s14, s3 ; GFX9-NEXT: s_cmp_ge_u32 s13, s7 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0 ; GFX9-NEXT: s_add_i32 s3, s12, 1 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: s_cselect_b32 s3, s3, s12 ; GFX9-NEXT: s_sub_i32 s7, s13, s7 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: s_cselect_b32 s7, s7, s13 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_v4i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10 ; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX10-NEXT: s_sub_i32 s11, 0, s4 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s10, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX10-NEXT: s_mul_i32 s11, s11, s10 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: s_mul_hi_u32 s11, s10, s11 ; GFX10-NEXT: s_add_i32 s10, s10, s11 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: s_mul_hi_u32 s10, s0, s10 ; GFX10-NEXT: s_mul_i32 s11, s10, s4 ; GFX10-NEXT: s_sub_i32 s0, s0, s11 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cmp_ge_u32 s0, s4 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_add_i32 s12, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: v_readfirstlane_b32 s13, v0 ; GFX10-NEXT: s_cselect_b32 s10, s12, s10 ; GFX10-NEXT: s_sub_i32 s12, s0, s4 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1 ; GFX10-NEXT: s_cselect_b32 s11, s12, s0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX10-NEXT: s_cmp_ge_u32 s11, s4 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_add_i32 s0, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cselect_b32 s0, s0, s10 ; GFX10-NEXT: s_sub_i32 s4, s11, s4 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: s_cselect_b32 s4, s4, s11 ; GFX10-NEXT: s_sub_i32 s10, 0, s5 ; GFX10-NEXT: s_mul_i32 s10, s10, s13 ; GFX10-NEXT: s_mul_hi_u32 s10, s13, s10 ; GFX10-NEXT: s_add_i32 s13, s13, s10 ; GFX10-NEXT: s_mul_hi_u32 s10, s1, s13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v0 ; GFX10-NEXT: s_mul_i32 s11, s10, s5 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1 ; GFX10-NEXT: s_sub_i32 s1, s1, s11 ; GFX10-NEXT: s_cmp_ge_u32 s1, s5 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_add_i32 s12, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cselect_b32 s10, s12, s10 ; GFX10-NEXT: s_sub_i32 s12, s1, s5 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cselect_b32 s11, s12, s1 ; GFX10-NEXT: s_cmp_ge_u32 s11, s5 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_add_i32 s1, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cselect_b32 s1, s1, s10 ; GFX10-NEXT: s_sub_i32 s5, s11, s5 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cselect_b32 s5, s5, s11 ; GFX10-NEXT: s_sub_i32 s10, 0, s6 ; GFX10-NEXT: s_mul_i32 s10, s10, s13 ; GFX10-NEXT: s_mul_hi_u32 s10, s13, s10 ; GFX10-NEXT: s_add_i32 s13, s13, s10 ; GFX10-NEXT: s_mul_hi_u32 s10, s2, s13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v0 ; GFX10-NEXT: s_mul_i32 s11, s10, s6 ; GFX10-NEXT: s_sub_i32 s2, s2, s11 ; GFX10-NEXT: s_cmp_ge_u32 s2, s6 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_add_i32 s12, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cselect_b32 s10, s12, s10 ; GFX10-NEXT: s_sub_i32 s12, s2, s6 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cselect_b32 s11, s12, s2 ; GFX10-NEXT: s_cmp_ge_u32 s11, s6 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_add_i32 s2, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cselect_b32 s2, s2, s10 ; GFX10-NEXT: s_sub_i32 s6, s11, s6 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cselect_b32 s6, s6, s11 ; GFX10-NEXT: s_sub_i32 s10, 0, s7 ; GFX10-NEXT: s_mul_i32 s10, s10, s13 ; GFX10-NEXT: s_mul_hi_u32 s10, s13, s10 ; GFX10-NEXT: s_add_i32 s13, s13, s10 ; GFX10-NEXT: s_mul_hi_u32 s12, s3, s13 ; GFX10-NEXT: s_mul_i32 s10, s12, s7 ; GFX10-NEXT: s_sub_i32 s3, s3, s10 ; GFX10-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s3, s7 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10-NEXT: s_add_i32 s14, s12, 1 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cselect_b32 s12, s14, s12 ; GFX10-NEXT: s_sub_i32 s14, s3, s7 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cselect_b32 s13, s14, s3 ; GFX10-NEXT: s_cmp_ge_u32 s13, s7 ; GFX10-NEXT: s_cselect_b32 s14, 1, 0 ; GFX10-NEXT: s_add_i32 s3, s12, 1 ; GFX10-NEXT: s_cmp_lg_u32 s14, 0 ; GFX10-NEXT: s_cselect_b32 s3, s3, s12 ; GFX10-NEXT: s_sub_i32 s7, s13, s7 ; GFX10-NEXT: s_cmp_lg_u32 s14, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: s_cselect_b32 s7, s7, s13 ; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: v_mov_b32_e32 v4, s4 ; GFX10-NEXT: v_mov_b32_e32 v5, s5 ; GFX10-NEXT: v_mov_b32_e32 v6, s6 ; GFX10-NEXT: v_mov_b32_e32 v7, s7 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9] ; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[10:11] ; GFX10-NEXT: s_endpgm %div = udiv <4 x i32> %x, %y store <4 x i32> %div, ptr addrspace(1) %out0 %rem = urem <4 x i32> %x, %y store <4 x i32> %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i64> %x, <2 x i64> %y) { ; GFX8-LABEL: udivrem_v2i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_load_dwordx4 s[12:15], s[8:9], 0x20 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s13 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s12 ; GFX8-NEXT: s_sub_u32 s10, 0, s12 ; GFX8-NEXT: s_subb_u32 s11, 0, s13 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_hi_u32 v2, s10, v0 ; GFX8-NEXT: v_readfirstlane_b32 s1, v0 ; GFX8-NEXT: s_mul_i32 s2, s10, s1 ; GFX8-NEXT: v_readfirstlane_b32 s16, v1 ; GFX8-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX8-NEXT: s_mul_i32 s0, s10, s16 ; GFX8-NEXT: s_mul_i32 s4, s16, s2 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, s2 ; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: s_mul_i32 s3, s11, s1 ; GFX8-NEXT: s_add_u32 s0, s0, s2 ; GFX8-NEXT: s_add_u32 s0, s3, s0 ; GFX8-NEXT: v_readfirstlane_b32 s2, v3 ; GFX8-NEXT: s_mul_i32 s5, s1, s0 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s0 ; GFX8-NEXT: s_add_u32 s2, s2, s5 ; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_add_u32 s2, s2, s4 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: v_readfirstlane_b32 s3, v4 ; GFX8-NEXT: s_add_i32 s5, s5, s2 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: s_mul_i32 s4, s16, s0 ; GFX8-NEXT: s_add_u32 s2, s3, s2 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 ; GFX8-NEXT: s_add_u32 s2, s2, s4 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s0 ; GFX8-NEXT: s_add_i32 s3, s3, s4 ; GFX8-NEXT: s_add_u32 s0, s2, s5 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: s_add_i32 s3, s3, s2 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: s_add_i32 s17, s2, s3 ; GFX8-NEXT: s_add_u32 s18, s1, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s18 ; GFX8-NEXT: v_mul_hi_u32 v0, s10, v0 ; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX8-NEXT: s_mul_i32 s9, s10, s18 ; GFX8-NEXT: s_addc_u32 s8, s16, s17 ; GFX8-NEXT: v_readfirstlane_b32 s16, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s9 ; GFX8-NEXT: v_mul_hi_u32 v1, s18, v0 ; GFX8-NEXT: s_mul_i32 s10, s10, s8 ; GFX8-NEXT: s_add_u32 s10, s10, s16 ; GFX8-NEXT: s_mul_i32 s11, s11, s18 ; GFX8-NEXT: s_add_u32 s10, s11, s10 ; GFX8-NEXT: v_readfirstlane_b32 s11, v1 ; GFX8-NEXT: v_mov_b32_e32 v1, s10 ; GFX8-NEXT: s_mul_i32 s16, s18, s10 ; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX8-NEXT: v_mul_hi_u32 v2, s18, v1 ; GFX8-NEXT: s_mul_i32 s9, s8, s9 ; GFX8-NEXT: s_add_u32 s11, s11, s16 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_add_u32 s9, s11, s9 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s16, s16, s9 ; GFX8-NEXT: v_readfirstlane_b32 s9, v0 ; GFX8-NEXT: v_readfirstlane_b32 s11, v2 ; GFX8-NEXT: s_mul_i32 s10, s8, s10 ; GFX8-NEXT: s_add_u32 s9, s9, s11 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_u32 s9, s9, s10 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, s8, v1 ; GFX8-NEXT: s_add_i32 s10, s11, s10 ; GFX8-NEXT: s_add_u32 s9, s9, s16 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_i32 s10, s10, s11 ; GFX8-NEXT: v_readfirstlane_b32 s11, v0 ; GFX8-NEXT: s_add_i32 s11, s11, s10 ; GFX8-NEXT: s_add_u32 s9, s18, s9 ; GFX8-NEXT: v_mov_b32_e32 v0, s9 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX8-NEXT: s_addc_u32 s8, s8, s11 ; GFX8-NEXT: v_mov_b32_e32 v1, s8 ; GFX8-NEXT: s_mul_i32 s11, s4, s8 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s5 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s9 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v1 ; GFX8-NEXT: s_mul_i32 s16, s5, s9 ; GFX8-NEXT: s_add_u32 s10, s10, s11 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_u32 s10, s10, s16 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s11, s9 ; GFX8-NEXT: v_readfirstlane_b32 s9, v0 ; GFX8-NEXT: v_readfirstlane_b32 s10, v2 ; GFX8-NEXT: s_mul_i32 s8, s5, s8 ; GFX8-NEXT: s_add_u32 s9, s9, s10 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_u32 s8, s9, s8 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s9, s10, s9 ; GFX8-NEXT: s_add_u32 s8, s8, s11 ; GFX8-NEXT: v_mul_hi_u32 v0, s5, v1 ; GFX8-NEXT: v_mov_b32_e32 v1, s8 ; GFX8-NEXT: v_mul_hi_u32 v1, s12, v1 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_i32 s9, s9, s10 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: s_add_i32 s9, s10, s9 ; GFX8-NEXT: v_readfirstlane_b32 s11, v1 ; GFX8-NEXT: s_mul_i32 s16, s12, s9 ; GFX8-NEXT: s_add_u32 s11, s16, s11 ; GFX8-NEXT: s_mul_i32 s16, s13, s8 ; GFX8-NEXT: s_mul_i32 s10, s12, s8 ; GFX8-NEXT: s_add_u32 s16, s16, s11 ; GFX8-NEXT: s_sub_u32 s10, s4, s10 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_subb_u32 s11, s5, s16 ; GFX8-NEXT: s_sub_i32 s5, s5, s16 ; GFX8-NEXT: s_cmp_ge_u32 s11, s13 ; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_cmp_ge_u32 s10, s12 ; GFX8-NEXT: s_cselect_b32 s17, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s11, s13 ; GFX8-NEXT: s_cselect_b32 s20, s17, s16 ; GFX8-NEXT: s_sub_u32 s16, s10, s12 ; GFX8-NEXT: s_cselect_b32 s21, 1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_subb_u32 s22, s5, s13 ; GFX8-NEXT: s_cmp_lg_u32 s21, 0 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s15 ; GFX8-NEXT: s_subb_u32 s17, s22, 0 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s14 ; GFX8-NEXT: s_add_u32 s4, s8, 1 ; GFX8-NEXT: s_addc_u32 s5, s9, 0 ; GFX8-NEXT: s_cmp_ge_u32 s17, s13 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: s_cmp_ge_u32 s16, s12 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s17, s13 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_cselect_b32 s23, s19, s18 ; GFX8-NEXT: s_add_u32 s18, s4, 1 ; GFX8-NEXT: s_addc_u32 s19, s5, 0 ; GFX8-NEXT: s_sub_u32 s12, s16, s12 ; GFX8-NEXT: s_cselect_b32 s24, 1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s21, 0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: s_subb_u32 s13, s22, s13 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: s_cmp_lg_u32 s24, 0 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: s_subb_u32 s13, s13, 0 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: s_cmp_lg_u32 s23, 0 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: s_cselect_b64 s[4:5], s[18:19], s[4:5] ; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] ; GFX8-NEXT: s_cmp_lg_u32 s23, 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], s[16:17] ; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX8-NEXT: s_sub_u32 s11, 0, s14 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_hi_u32 v2, s11, v0 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: s_mul_i32 s16, s11, s10 ; GFX8-NEXT: v_readfirstlane_b32 s12, v1 ; GFX8-NEXT: v_readfirstlane_b32 s17, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v0, s16 ; GFX8-NEXT: s_subb_u32 s13, 0, s15 ; GFX8-NEXT: s_mul_i32 s18, s11, s12 ; GFX8-NEXT: s_add_u32 s17, s18, s17 ; GFX8-NEXT: s_mul_i32 s18, s13, s10 ; GFX8-NEXT: s_add_u32 s17, s18, s17 ; GFX8-NEXT: v_readfirstlane_b32 s18, v2 ; GFX8-NEXT: s_mul_i32 s19, s10, s17 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, s16 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s17 ; GFX8-NEXT: s_mul_i32 s20, s12, s16 ; GFX8-NEXT: s_add_u32 s18, s18, s19 ; GFX8-NEXT: s_cselect_b32 s19, 1, 0 ; GFX8-NEXT: s_add_u32 s18, s18, s20 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_add_i32 s19, s19, s16 ; GFX8-NEXT: v_readfirstlane_b32 s16, v2 ; GFX8-NEXT: v_readfirstlane_b32 s18, v0 ; GFX8-NEXT: s_mul_i32 s20, s12, s17 ; GFX8-NEXT: s_add_u32 s16, s16, s18 ; GFX8-NEXT: s_cselect_b32 s18, 1, 0 ; GFX8-NEXT: s_add_u32 s16, s16, s20 ; GFX8-NEXT: s_cselect_b32 s20, 1, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s17 ; GFX8-NEXT: s_add_i32 s18, s18, s20 ; GFX8-NEXT: s_add_u32 s16, s16, s19 ; GFX8-NEXT: s_cselect_b32 s17, 1, 0 ; GFX8-NEXT: s_add_i32 s18, s18, s17 ; GFX8-NEXT: v_readfirstlane_b32 s17, v0 ; GFX8-NEXT: s_add_i32 s17, s17, s18 ; GFX8-NEXT: s_add_u32 s10, s10, s16 ; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX8-NEXT: s_mul_i32 s16, s11, s10 ; GFX8-NEXT: s_addc_u32 s12, s12, s17 ; GFX8-NEXT: s_mul_i32 s11, s11, s12 ; GFX8-NEXT: v_readfirstlane_b32 s17, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s16 ; GFX8-NEXT: v_mul_hi_u32 v1, s10, v0 ; GFX8-NEXT: s_add_u32 s11, s11, s17 ; GFX8-NEXT: s_mul_i32 s13, s13, s10 ; GFX8-NEXT: s_add_u32 s11, s13, s11 ; GFX8-NEXT: v_readfirstlane_b32 s13, v1 ; GFX8-NEXT: v_mov_b32_e32 v1, s11 ; GFX8-NEXT: s_mul_i32 s17, s10, s11 ; GFX8-NEXT: v_mul_hi_u32 v0, s12, v0 ; GFX8-NEXT: v_mul_hi_u32 v2, s10, v1 ; GFX8-NEXT: s_mul_i32 s16, s12, s16 ; GFX8-NEXT: s_add_u32 s13, s13, s17 ; GFX8-NEXT: s_cselect_b32 s17, 1, 0 ; GFX8-NEXT: s_add_u32 s13, s13, s16 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_add_i32 s17, s17, s13 ; GFX8-NEXT: v_readfirstlane_b32 s13, v0 ; GFX8-NEXT: v_readfirstlane_b32 s16, v2 ; GFX8-NEXT: s_mul_i32 s11, s12, s11 ; GFX8-NEXT: s_add_u32 s13, s13, s16 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_add_u32 s11, s13, s11 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: v_mul_hi_u32 v0, s12, v1 ; GFX8-NEXT: s_add_i32 s13, s16, s13 ; GFX8-NEXT: s_add_u32 s11, s11, s17 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_add_i32 s13, s13, s16 ; GFX8-NEXT: v_readfirstlane_b32 s16, v0 ; GFX8-NEXT: s_add_i32 s16, s16, s13 ; GFX8-NEXT: s_add_u32 s10, s10, s11 ; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mul_hi_u32 v0, s6, v0 ; GFX8-NEXT: s_addc_u32 s11, s12, s16 ; GFX8-NEXT: v_mov_b32_e32 v1, s11 ; GFX8-NEXT: s_mul_i32 s13, s6, s11 ; GFX8-NEXT: v_readfirstlane_b32 s12, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s7 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s10 ; GFX8-NEXT: v_mul_hi_u32 v2, s6, v1 ; GFX8-NEXT: s_mul_i32 s16, s7, s10 ; GFX8-NEXT: s_add_u32 s12, s12, s13 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_add_u32 s12, s12, s16 ; GFX8-NEXT: s_cselect_b32 s10, 1, 0 ; GFX8-NEXT: s_add_i32 s13, s13, s10 ; GFX8-NEXT: v_readfirstlane_b32 s10, v0 ; GFX8-NEXT: v_readfirstlane_b32 s12, v2 ; GFX8-NEXT: s_mul_i32 s11, s7, s11 ; GFX8-NEXT: s_add_u32 s10, s10, s12 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_add_u32 s10, s10, s11 ; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s12, s11 ; GFX8-NEXT: s_add_u32 s10, s10, s13 ; GFX8-NEXT: v_mul_hi_u32 v0, s7, v1 ; GFX8-NEXT: v_mov_b32_e32 v1, s10 ; GFX8-NEXT: v_mul_hi_u32 v1, s14, v1 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_add_i32 s11, s11, s12 ; GFX8-NEXT: v_readfirstlane_b32 s12, v0 ; GFX8-NEXT: s_add_i32 s11, s12, s11 ; GFX8-NEXT: v_readfirstlane_b32 s13, v1 ; GFX8-NEXT: s_mul_i32 s16, s14, s11 ; GFX8-NEXT: s_add_u32 s13, s16, s13 ; GFX8-NEXT: s_mul_i32 s16, s15, s10 ; GFX8-NEXT: s_mul_i32 s12, s14, s10 ; GFX8-NEXT: s_add_u32 s16, s16, s13 ; GFX8-NEXT: s_sub_u32 s12, s6, s12 ; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: s_subb_u32 s13, s7, s16 ; GFX8-NEXT: s_sub_i32 s7, s7, s16 ; GFX8-NEXT: s_cmp_ge_u32 s13, s15 ; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_cmp_ge_u32 s12, s14 ; GFX8-NEXT: s_cselect_b32 s17, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s13, s15 ; GFX8-NEXT: s_cselect_b32 s20, s17, s16 ; GFX8-NEXT: s_sub_u32 s16, s12, s14 ; GFX8-NEXT: s_cselect_b32 s21, 1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_subb_u32 s22, s7, s15 ; GFX8-NEXT: s_cmp_lg_u32 s21, 0 ; GFX8-NEXT: s_subb_u32 s17, s22, 0 ; GFX8-NEXT: s_add_u32 s6, s10, 1 ; GFX8-NEXT: s_addc_u32 s7, s11, 0 ; GFX8-NEXT: s_cmp_ge_u32 s17, s15 ; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: s_cmp_ge_u32 s16, s14 ; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s17, s15 ; GFX8-NEXT: s_cselect_b32 s23, s19, s18 ; GFX8-NEXT: s_add_u32 s18, s6, 1 ; GFX8-NEXT: s_addc_u32 s19, s7, 0 ; GFX8-NEXT: s_sub_u32 s14, s16, s14 ; GFX8-NEXT: s_cselect_b32 s24, 1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s21, 0 ; GFX8-NEXT: s_subb_u32 s15, s22, s15 ; GFX8-NEXT: s_cmp_lg_u32 s24, 0 ; GFX8-NEXT: s_subb_u32 s15, s15, 0 ; GFX8-NEXT: s_cmp_lg_u32 s23, 0 ; GFX8-NEXT: s_cselect_b64 s[6:7], s[18:19], s[6:7] ; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] ; GFX8-NEXT: s_cmp_lg_u32 s23, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v5, s1 ; GFX8-NEXT: s_cselect_b64 s[10:11], s[14:15], s[16:17] ; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s6 ; GFX8-NEXT: v_mov_b32_e32 v3, s7 ; GFX8-NEXT: v_mov_b32_e32 v4, s0 ; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13] ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NEXT: v_mov_b32_e32 v5, s3 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: v_mov_b32_e32 v1, s9 ; GFX8-NEXT: v_mov_b32_e32 v2, s10 ; GFX8-NEXT: v_mov_b32_e32 v3, s11 ; GFX8-NEXT: v_mov_b32_e32 v4, s2 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_v2i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx4 s[12:15], s[8:9], 0x20 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s13 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s12 ; GFX9-NEXT: s_sub_u32 s8, 0, s12 ; GFX9-NEXT: s_subb_u32 s9, 0, s13 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s10, v1 ; GFX9-NEXT: v_readfirstlane_b32 s16, v0 ; GFX9-NEXT: s_mul_i32 s11, s8, s10 ; GFX9-NEXT: s_mul_hi_u32 s18, s8, s16 ; GFX9-NEXT: s_mul_i32 s19, s9, s16 ; GFX9-NEXT: s_add_u32 s11, s11, s18 ; GFX9-NEXT: s_mul_i32 s17, s8, s16 ; GFX9-NEXT: s_add_u32 s11, s19, s11 ; GFX9-NEXT: s_mul_hi_u32 s18, s16, s17 ; GFX9-NEXT: s_mul_i32 s19, s16, s11 ; GFX9-NEXT: s_mul_i32 s20, s10, s17 ; GFX9-NEXT: s_add_u32 s18, s18, s19 ; GFX9-NEXT: s_cselect_b32 s19, 1, 0 ; GFX9-NEXT: s_add_u32 s18, s18, s20 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_mul_hi_u32 s17, s10, s17 ; GFX9-NEXT: s_add_i32 s19, s19, s18 ; GFX9-NEXT: s_mul_hi_u32 s18, s16, s11 ; GFX9-NEXT: s_mul_i32 s20, s10, s11 ; GFX9-NEXT: s_add_u32 s17, s17, s18 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_add_u32 s17, s17, s20 ; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_add_i32 s18, s18, s20 ; GFX9-NEXT: s_add_u32 s17, s17, s19 ; GFX9-NEXT: s_cselect_b32 s19, 1, 0 ; GFX9-NEXT: s_add_i32 s18, s18, s19 ; GFX9-NEXT: s_mul_hi_u32 s11, s10, s11 ; GFX9-NEXT: s_add_i32 s11, s11, s18 ; GFX9-NEXT: s_add_u32 s16, s16, s17 ; GFX9-NEXT: s_addc_u32 s10, s10, s11 ; GFX9-NEXT: s_mul_i32 s11, s8, s16 ; GFX9-NEXT: s_mul_hi_u32 s17, s8, s16 ; GFX9-NEXT: s_mul_i32 s8, s8, s10 ; GFX9-NEXT: s_add_u32 s8, s8, s17 ; GFX9-NEXT: s_mul_i32 s9, s9, s16 ; GFX9-NEXT: s_add_u32 s8, s9, s8 ; GFX9-NEXT: s_mul_hi_u32 s9, s16, s11 ; GFX9-NEXT: s_mul_i32 s17, s16, s8 ; GFX9-NEXT: s_mul_i32 s18, s10, s11 ; GFX9-NEXT: s_add_u32 s9, s9, s17 ; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_add_u32 s9, s9, s18 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s17, s17, s9 ; GFX9-NEXT: s_mul_hi_u32 s9, s10, s11 ; GFX9-NEXT: s_mul_hi_u32 s11, s16, s8 ; GFX9-NEXT: s_mul_i32 s18, s10, s8 ; GFX9-NEXT: s_add_u32 s9, s9, s11 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_u32 s9, s9, s18 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s11, s18 ; GFX9-NEXT: s_add_u32 s9, s9, s17 ; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s11, s17 ; GFX9-NEXT: s_mul_hi_u32 s8, s10, s8 ; GFX9-NEXT: s_add_i32 s8, s8, s11 ; GFX9-NEXT: s_add_u32 s9, s16, s9 ; GFX9-NEXT: s_addc_u32 s10, s10, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s4, s9 ; GFX9-NEXT: s_mul_i32 s11, s4, s10 ; GFX9-NEXT: s_mul_i32 s16, s5, s9 ; GFX9-NEXT: s_add_u32 s8, s8, s11 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_u32 s8, s8, s16 ; GFX9-NEXT: s_cselect_b32 s8, 1, 0 ; GFX9-NEXT: s_add_i32 s11, s11, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s5, s9 ; GFX9-NEXT: s_mul_hi_u32 s9, s4, s10 ; GFX9-NEXT: s_mul_i32 s16, s5, s10 ; GFX9-NEXT: s_add_u32 s8, s8, s9 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_u32 s8, s8, s16 ; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_add_i32 s9, s9, s16 ; GFX9-NEXT: s_add_u32 s8, s8, s11 ; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_add_i32 s9, s9, s11 ; GFX9-NEXT: s_mul_hi_u32 s10, s5, s10 ; GFX9-NEXT: s_add_i32 s9, s10, s9 ; GFX9-NEXT: s_mul_hi_u32 s11, s12, s8 ; GFX9-NEXT: s_mul_i32 s16, s12, s9 ; GFX9-NEXT: s_add_u32 s11, s16, s11 ; GFX9-NEXT: s_mul_i32 s16, s13, s8 ; GFX9-NEXT: s_mul_i32 s10, s12, s8 ; GFX9-NEXT: s_add_u32 s16, s16, s11 ; GFX9-NEXT: s_sub_u32 s10, s4, s10 ; GFX9-NEXT: s_cselect_b32 s4, 1, 0 ; GFX9-NEXT: s_subb_u32 s11, s5, s16 ; GFX9-NEXT: s_sub_i32 s5, s5, s16 ; GFX9-NEXT: s_cmp_ge_u32 s11, s13 ; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_cmp_ge_u32 s10, s12 ; GFX9-NEXT: s_cselect_b32 s17, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s11, s13 ; GFX9-NEXT: s_cselect_b32 s20, s17, s16 ; GFX9-NEXT: s_sub_u32 s16, s10, s12 ; GFX9-NEXT: s_cselect_b32 s21, 1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s4, 0 ; GFX9-NEXT: s_subb_u32 s22, s5, s13 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s15 ; GFX9-NEXT: s_cmp_lg_u32 s21, 0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s14 ; GFX9-NEXT: s_subb_u32 s17, s22, 0 ; GFX9-NEXT: s_add_u32 s4, s8, 1 ; GFX9-NEXT: s_addc_u32 s5, s9, 0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: s_cmp_ge_u32 s17, s13 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_cmp_ge_u32 s16, s12 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s17, s13 ; GFX9-NEXT: s_cselect_b32 s23, s19, s18 ; GFX9-NEXT: s_add_u32 s18, s4, 1 ; GFX9-NEXT: s_addc_u32 s19, s5, 0 ; GFX9-NEXT: s_sub_u32 s12, s16, s12 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: s_cselect_b32 s24, 1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s21, 0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: s_subb_u32 s13, s22, s13 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: s_cmp_lg_u32 s24, 0 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: s_subb_u32 s13, s13, 0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: s_cmp_lg_u32 s23, 0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: s_cselect_b64 s[4:5], s[18:19], s[4:5] ; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] ; GFX9-NEXT: s_cmp_lg_u32 s23, 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], s[16:17] ; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX9-NEXT: v_readfirstlane_b32 s10, v0 ; GFX9-NEXT: v_readfirstlane_b32 s11, v1 ; GFX9-NEXT: s_sub_u32 s12, 0, s14 ; GFX9-NEXT: s_subb_u32 s13, 0, s15 ; GFX9-NEXT: s_mul_hi_u32 s17, s12, s10 ; GFX9-NEXT: s_mul_i32 s18, s12, s11 ; GFX9-NEXT: s_add_u32 s17, s18, s17 ; GFX9-NEXT: s_mul_i32 s18, s13, s10 ; GFX9-NEXT: s_mul_i32 s16, s12, s10 ; GFX9-NEXT: s_add_u32 s17, s18, s17 ; GFX9-NEXT: s_mul_hi_u32 s18, s10, s16 ; GFX9-NEXT: s_mul_i32 s19, s10, s17 ; GFX9-NEXT: s_mul_i32 s20, s11, s16 ; GFX9-NEXT: s_add_u32 s18, s18, s19 ; GFX9-NEXT: s_cselect_b32 s19, 1, 0 ; GFX9-NEXT: s_add_u32 s18, s18, s20 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_add_i32 s19, s19, s18 ; GFX9-NEXT: s_mul_hi_u32 s16, s11, s16 ; GFX9-NEXT: s_mul_hi_u32 s18, s10, s17 ; GFX9-NEXT: s_mul_i32 s20, s11, s17 ; GFX9-NEXT: s_add_u32 s16, s16, s18 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_add_u32 s16, s16, s20 ; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_add_i32 s18, s18, s20 ; GFX9-NEXT: s_add_u32 s16, s16, s19 ; GFX9-NEXT: s_cselect_b32 s19, 1, 0 ; GFX9-NEXT: s_add_i32 s18, s18, s19 ; GFX9-NEXT: s_mul_hi_u32 s17, s11, s17 ; GFX9-NEXT: s_add_i32 s17, s17, s18 ; GFX9-NEXT: s_add_u32 s10, s10, s16 ; GFX9-NEXT: s_addc_u32 s11, s11, s17 ; GFX9-NEXT: s_mul_i32 s16, s12, s10 ; GFX9-NEXT: s_mul_hi_u32 s17, s12, s10 ; GFX9-NEXT: s_mul_i32 s12, s12, s11 ; GFX9-NEXT: s_add_u32 s12, s12, s17 ; GFX9-NEXT: s_mul_i32 s13, s13, s10 ; GFX9-NEXT: s_add_u32 s12, s13, s12 ; GFX9-NEXT: s_mul_hi_u32 s13, s10, s16 ; GFX9-NEXT: s_mul_i32 s17, s10, s12 ; GFX9-NEXT: s_mul_i32 s18, s11, s16 ; GFX9-NEXT: s_add_u32 s13, s13, s17 ; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_add_u32 s13, s13, s18 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s17, s17, s13 ; GFX9-NEXT: s_mul_hi_u32 s13, s11, s16 ; GFX9-NEXT: s_mul_hi_u32 s16, s10, s12 ; GFX9-NEXT: s_mul_i32 s18, s11, s12 ; GFX9-NEXT: s_add_u32 s13, s13, s16 ; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_add_u32 s13, s13, s18 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_add_i32 s16, s16, s18 ; GFX9-NEXT: s_add_u32 s13, s13, s17 ; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_add_i32 s16, s16, s17 ; GFX9-NEXT: s_mul_hi_u32 s12, s11, s12 ; GFX9-NEXT: s_add_i32 s12, s12, s16 ; GFX9-NEXT: s_add_u32 s10, s10, s13 ; GFX9-NEXT: s_addc_u32 s11, s11, s12 ; GFX9-NEXT: s_mul_hi_u32 s12, s6, s10 ; GFX9-NEXT: s_mul_i32 s13, s6, s11 ; GFX9-NEXT: s_mul_i32 s16, s7, s10 ; GFX9-NEXT: s_add_u32 s12, s12, s13 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_u32 s12, s12, s16 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: s_add_i32 s13, s13, s12 ; GFX9-NEXT: s_mul_hi_u32 s10, s7, s10 ; GFX9-NEXT: s_mul_hi_u32 s12, s6, s11 ; GFX9-NEXT: s_mul_i32 s16, s7, s11 ; GFX9-NEXT: s_add_u32 s10, s10, s12 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: s_add_u32 s10, s10, s16 ; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_add_i32 s12, s12, s16 ; GFX9-NEXT: s_add_u32 s10, s10, s13 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_add_i32 s12, s12, s13 ; GFX9-NEXT: s_mul_hi_u32 s11, s7, s11 ; GFX9-NEXT: s_add_i32 s11, s11, s12 ; GFX9-NEXT: s_mul_hi_u32 s13, s14, s10 ; GFX9-NEXT: s_mul_i32 s16, s14, s11 ; GFX9-NEXT: s_add_u32 s13, s16, s13 ; GFX9-NEXT: s_mul_i32 s16, s15, s10 ; GFX9-NEXT: s_mul_i32 s12, s14, s10 ; GFX9-NEXT: s_add_u32 s16, s16, s13 ; GFX9-NEXT: s_sub_u32 s12, s6, s12 ; GFX9-NEXT: s_cselect_b32 s6, 1, 0 ; GFX9-NEXT: s_subb_u32 s13, s7, s16 ; GFX9-NEXT: s_sub_i32 s7, s7, s16 ; GFX9-NEXT: s_cmp_ge_u32 s13, s15 ; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_cmp_ge_u32 s12, s14 ; GFX9-NEXT: s_cselect_b32 s17, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s13, s15 ; GFX9-NEXT: s_cselect_b32 s20, s17, s16 ; GFX9-NEXT: s_sub_u32 s16, s12, s14 ; GFX9-NEXT: s_cselect_b32 s21, 1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s6, 0 ; GFX9-NEXT: s_subb_u32 s22, s7, s15 ; GFX9-NEXT: s_cmp_lg_u32 s21, 0 ; GFX9-NEXT: s_subb_u32 s17, s22, 0 ; GFX9-NEXT: s_add_u32 s6, s10, 1 ; GFX9-NEXT: s_addc_u32 s7, s11, 0 ; GFX9-NEXT: s_cmp_ge_u32 s17, s15 ; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_cmp_ge_u32 s16, s14 ; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s17, s15 ; GFX9-NEXT: s_cselect_b32 s23, s19, s18 ; GFX9-NEXT: s_add_u32 s18, s6, 1 ; GFX9-NEXT: s_addc_u32 s19, s7, 0 ; GFX9-NEXT: s_sub_u32 s14, s16, s14 ; GFX9-NEXT: s_cselect_b32 s24, 1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s21, 0 ; GFX9-NEXT: s_subb_u32 s15, s22, s15 ; GFX9-NEXT: s_cmp_lg_u32 s24, 0 ; GFX9-NEXT: s_subb_u32 s15, s15, 0 ; GFX9-NEXT: s_cmp_lg_u32 s23, 0 ; GFX9-NEXT: s_cselect_b64 s[6:7], s[18:19], s[6:7] ; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] ; GFX9-NEXT: s_cmp_lg_u32 s23, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: s_cselect_b64 s[10:11], s[14:15], s[16:17] ; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s8 ; GFX9-NEXT: v_mov_b32_e32 v1, s9 ; GFX9-NEXT: v_mov_b32_e32 v2, s10 ; GFX9-NEXT: v_mov_b32_e32 v3, s11 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_v2i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_load_dwordx4 s[12:15], s[8:9], 0x20 ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s13 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s12 ; GFX10-NEXT: s_sub_u32 s10, 0, s12 ; GFX10-NEXT: s_subb_u32 s11, 0, s13 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s8, v1 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s15 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_mul_i32 s16, s10, s8 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 ; GFX10-NEXT: v_readfirstlane_b32 s9, v0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s14 ; GFX10-NEXT: s_mul_hi_u32 s18, s10, s9 ; GFX10-NEXT: s_mul_i32 s19, s11, s9 ; GFX10-NEXT: s_add_i32 s16, s18, s16 ; GFX10-NEXT: s_mul_i32 s17, s10, s9 ; GFX10-NEXT: s_add_i32 s16, s16, s19 ; GFX10-NEXT: s_mul_hi_u32 s18, s9, s17 ; GFX10-NEXT: s_mul_i32 s19, s9, s16 ; GFX10-NEXT: s_mul_i32 s20, s8, s17 ; GFX10-NEXT: s_add_u32 s18, s18, s19 ; GFX10-NEXT: s_cselect_b32 s19, 1, 0 ; GFX10-NEXT: s_add_u32 s18, s18, s20 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s17, s8, s17 ; GFX10-NEXT: s_mul_hi_u32 s21, s9, s16 ; GFX10-NEXT: s_add_i32 s19, s19, s18 ; GFX10-NEXT: s_mul_i32 s20, s8, s16 ; GFX10-NEXT: s_add_u32 s17, s17, s21 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_add_u32 s17, s17, s20 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s16, s8, s16 ; GFX10-NEXT: s_add_i32 s18, s18, s20 ; GFX10-NEXT: s_add_u32 s17, s17, s19 ; GFX10-NEXT: s_cselect_b32 s19, 1, 0 ; GFX10-NEXT: v_add_f32_e32 v0, v1, v0 ; GFX10-NEXT: s_add_i32 s18, s18, s19 ; GFX10-NEXT: s_add_i32 s16, s16, s18 ; GFX10-NEXT: s_add_u32 s9, s9, s17 ; GFX10-NEXT: s_addc_u32 s8, s8, s16 ; GFX10-NEXT: s_mul_i32 s16, s10, s9 ; GFX10-NEXT: s_mul_hi_u32 s17, s10, s9 ; GFX10-NEXT: s_mul_i32 s10, s10, s8 ; GFX10-NEXT: s_mul_i32 s11, s11, s9 ; GFX10-NEXT: s_add_i32 s10, s17, s10 ; GFX10-NEXT: s_mul_hi_u32 s18, s9, s16 ; GFX10-NEXT: s_add_i32 s10, s10, s11 ; GFX10-NEXT: s_mul_i32 s17, s8, s16 ; GFX10-NEXT: s_mul_hi_u32 s11, s8, s16 ; GFX10-NEXT: s_mul_i32 s16, s9, s10 ; GFX10-NEXT: s_mul_hi_u32 s19, s9, s10 ; GFX10-NEXT: s_add_u32 s16, s18, s16 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_add_u32 s16, s16, s17 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_mul_i32 s17, s8, s10 ; GFX10-NEXT: s_add_i32 s18, s18, s16 ; GFX10-NEXT: s_add_u32 s11, s11, s19 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_add_u32 s11, s11, s17 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s10, s8, s10 ; GFX10-NEXT: s_add_i32 s16, s16, s17 ; GFX10-NEXT: s_add_u32 s11, s11, s18 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: s_add_i32 s16, s16, s17 ; GFX10-NEXT: s_add_i32 s10, s10, s16 ; GFX10-NEXT: s_add_u32 s9, s9, s11 ; GFX10-NEXT: s_addc_u32 s10, s8, s10 ; GFX10-NEXT: s_mul_hi_u32 s8, s4, s9 ; GFX10-NEXT: s_mul_i32 s16, s4, s10 ; GFX10-NEXT: s_mul_i32 s11, s5, s9 ; GFX10-NEXT: s_add_u32 s8, s8, s16 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_add_u32 s8, s8, s11 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s9, s5, s9 ; GFX10-NEXT: s_mul_hi_u32 s17, s4, s10 ; GFX10-NEXT: s_add_i32 s16, s16, s8 ; GFX10-NEXT: s_mul_i32 s11, s5, s10 ; GFX10-NEXT: s_add_u32 s8, s9, s17 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: s_add_u32 s8, s8, s11 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s10, s5, s10 ; GFX10-NEXT: s_add_i32 s9, s9, s11 ; GFX10-NEXT: s_add_u32 s8, s8, s16 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_mul_i32 s16, s13, s8 ; GFX10-NEXT: s_add_i32 s9, s9, s11 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: s_add_i32 s9, s10, s9 ; GFX10-NEXT: s_mul_hi_u32 s10, s12, s8 ; GFX10-NEXT: s_mul_i32 s11, s12, s9 ; GFX10-NEXT: s_add_i32 s10, s10, s11 ; GFX10-NEXT: s_mul_i32 s11, s12, s8 ; GFX10-NEXT: s_add_i32 s16, s10, s16 ; GFX10-NEXT: s_sub_u32 s10, s4, s11 ; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: s_subb_u32 s11, s5, s16 ; GFX10-NEXT: s_sub_i32 s5, s5, s16 ; GFX10-NEXT: s_cmp_ge_u32 s11, s13 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_cmp_ge_u32 s10, s12 ; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s11, s13 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: s_cselect_b32 s20, s17, s16 ; GFX10-NEXT: s_sub_u32 s16, s10, s12 ; GFX10-NEXT: s_cselect_b32 s21, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: s_subb_u32 s22, s5, s13 ; GFX10-NEXT: s_cmp_lg_u32 s21, 0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: s_subb_u32 s17, s22, 0 ; GFX10-NEXT: s_add_u32 s4, s8, 1 ; GFX10-NEXT: s_addc_u32 s5, s9, 0 ; GFX10-NEXT: s_cmp_ge_u32 s17, s13 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: s_cmp_ge_u32 s16, s12 ; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s17, s13 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cselect_b32 s23, s19, s18 ; GFX10-NEXT: s_add_u32 s18, s4, 1 ; GFX10-NEXT: s_addc_u32 s19, s5, 0 ; GFX10-NEXT: s_sub_u32 s12, s16, s12 ; GFX10-NEXT: s_cselect_b32 s24, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s21, 0 ; GFX10-NEXT: s_subb_u32 s13, s22, s13 ; GFX10-NEXT: s_cmp_lg_u32 s24, 0 ; GFX10-NEXT: s_subb_u32 s13, s13, 0 ; GFX10-NEXT: s_cmp_lg_u32 s23, 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[18:19], s[4:5] ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: v_readfirstlane_b32 s18, v0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] ; GFX10-NEXT: s_cmp_lg_u32 s23, 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[12:13], s[16:17] ; GFX10-NEXT: v_readfirstlane_b32 s12, v1 ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX10-NEXT: s_sub_u32 s10, 0, s14 ; GFX10-NEXT: s_subb_u32 s11, 0, s15 ; GFX10-NEXT: s_mul_hi_u32 s16, s10, s18 ; GFX10-NEXT: s_mul_i32 s17, s10, s12 ; GFX10-NEXT: s_mul_i32 s19, s11, s18 ; GFX10-NEXT: s_add_i32 s16, s16, s17 ; GFX10-NEXT: s_mul_i32 s13, s10, s18 ; GFX10-NEXT: s_add_i32 s16, s16, s19 ; GFX10-NEXT: s_mul_hi_u32 s17, s18, s13 ; GFX10-NEXT: s_mul_i32 s19, s18, s16 ; GFX10-NEXT: s_mul_i32 s20, s12, s13 ; GFX10-NEXT: s_add_u32 s17, s17, s19 ; GFX10-NEXT: s_cselect_b32 s19, 1, 0 ; GFX10-NEXT: s_add_u32 s17, s17, s20 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s13, s12, s13 ; GFX10-NEXT: s_mul_hi_u32 s21, s18, s16 ; GFX10-NEXT: s_add_i32 s19, s19, s17 ; GFX10-NEXT: s_mul_i32 s20, s12, s16 ; GFX10-NEXT: s_add_u32 s13, s13, s21 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_add_u32 s13, s13, s20 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s16, s12, s16 ; GFX10-NEXT: s_add_i32 s17, s17, s20 ; GFX10-NEXT: s_add_u32 s13, s13, s19 ; GFX10-NEXT: s_cselect_b32 s19, 1, 0 ; GFX10-NEXT: s_add_i32 s17, s17, s19 ; GFX10-NEXT: s_add_i32 s16, s16, s17 ; GFX10-NEXT: s_add_u32 s13, s18, s13 ; GFX10-NEXT: s_addc_u32 s12, s12, s16 ; GFX10-NEXT: s_mul_i32 s16, s10, s13 ; GFX10-NEXT: s_mul_hi_u32 s17, s10, s13 ; GFX10-NEXT: s_mul_i32 s10, s10, s12 ; GFX10-NEXT: s_mul_i32 s11, s11, s13 ; GFX10-NEXT: s_add_i32 s10, s17, s10 ; GFX10-NEXT: s_mul_hi_u32 s18, s13, s16 ; GFX10-NEXT: s_add_i32 s10, s10, s11 ; GFX10-NEXT: s_mul_i32 s17, s12, s16 ; GFX10-NEXT: s_mul_hi_u32 s11, s12, s16 ; GFX10-NEXT: s_mul_i32 s16, s13, s10 ; GFX10-NEXT: s_mul_hi_u32 s19, s13, s10 ; GFX10-NEXT: s_add_u32 s16, s18, s16 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_add_u32 s16, s16, s17 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_mul_i32 s17, s12, s10 ; GFX10-NEXT: s_add_i32 s18, s18, s16 ; GFX10-NEXT: s_add_u32 s11, s11, s19 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_add_u32 s11, s11, s17 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s10, s12, s10 ; GFX10-NEXT: s_add_i32 s16, s16, s17 ; GFX10-NEXT: s_add_u32 s11, s11, s18 ; GFX10-NEXT: s_cselect_b32 s17, 1, 0 ; GFX10-NEXT: s_add_i32 s16, s16, s17 ; GFX10-NEXT: s_add_i32 s10, s10, s16 ; GFX10-NEXT: s_add_u32 s11, s13, s11 ; GFX10-NEXT: s_addc_u32 s12, s12, s10 ; GFX10-NEXT: s_mul_hi_u32 s10, s6, s11 ; GFX10-NEXT: s_mul_i32 s16, s6, s12 ; GFX10-NEXT: s_mul_i32 s13, s7, s11 ; GFX10-NEXT: s_add_u32 s10, s10, s16 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_add_u32 s10, s10, s13 ; GFX10-NEXT: s_cselect_b32 s10, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s11, s7, s11 ; GFX10-NEXT: s_mul_hi_u32 s17, s6, s12 ; GFX10-NEXT: s_add_i32 s16, s16, s10 ; GFX10-NEXT: s_mul_i32 s13, s7, s12 ; GFX10-NEXT: s_add_u32 s10, s11, s17 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_add_u32 s10, s10, s13 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10-NEXT: s_mul_hi_u32 s12, s7, s12 ; GFX10-NEXT: s_add_i32 s11, s11, s13 ; GFX10-NEXT: s_add_u32 s10, s10, s16 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10-NEXT: s_mul_i32 s16, s15, s10 ; GFX10-NEXT: s_add_i32 s11, s11, s13 ; GFX10-NEXT: s_add_i32 s11, s12, s11 ; GFX10-NEXT: s_mul_hi_u32 s12, s14, s10 ; GFX10-NEXT: s_mul_i32 s13, s14, s11 ; GFX10-NEXT: s_add_i32 s12, s12, s13 ; GFX10-NEXT: s_mul_i32 s13, s14, s10 ; GFX10-NEXT: s_add_i32 s16, s12, s16 ; GFX10-NEXT: s_sub_u32 s12, s6, s13 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: s_subb_u32 s13, s7, s16 ; GFX10-NEXT: s_sub_i32 s7, s7, s16 ; GFX10-NEXT: s_cmp_ge_u32 s13, s15 ; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_cmp_ge_u32 s12, s14 ; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s13, s15 ; GFX10-NEXT: s_cselect_b32 s20, s17, s16 ; GFX10-NEXT: s_sub_u32 s16, s12, s14 ; GFX10-NEXT: s_cselect_b32 s21, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 ; GFX10-NEXT: s_subb_u32 s22, s7, s15 ; GFX10-NEXT: s_cmp_lg_u32 s21, 0 ; GFX10-NEXT: s_subb_u32 s17, s22, 0 ; GFX10-NEXT: s_add_u32 s6, s10, 1 ; GFX10-NEXT: s_addc_u32 s7, s11, 0 ; GFX10-NEXT: s_cmp_ge_u32 s17, s15 ; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: s_cmp_ge_u32 s16, s14 ; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s17, s15 ; GFX10-NEXT: s_cselect_b32 s23, s19, s18 ; GFX10-NEXT: s_add_u32 s18, s6, 1 ; GFX10-NEXT: s_addc_u32 s19, s7, 0 ; GFX10-NEXT: s_sub_u32 s14, s16, s14 ; GFX10-NEXT: s_cselect_b32 s24, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s21, 0 ; GFX10-NEXT: s_subb_u32 s15, s22, s15 ; GFX10-NEXT: s_cmp_lg_u32 s24, 0 ; GFX10-NEXT: s_subb_u32 s15, s15, 0 ; GFX10-NEXT: s_cmp_lg_u32 s23, 0 ; GFX10-NEXT: s_cselect_b64 s[6:7], s[18:19], s[6:7] ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11] ; GFX10-NEXT: s_cmp_lg_u32 s23, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: s_cselect_b64 s[10:11], s[14:15], s[16:17] ; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13] ; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v3, s7 ; GFX10-NEXT: v_mov_b32_e32 v4, s8 ; GFX10-NEXT: v_mov_b32_e32 v5, s9 ; GFX10-NEXT: v_mov_b32_e32 v6, s10 ; GFX10-NEXT: v_mov_b32_e32 v7, s11 ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] ; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv <2 x i64> %x, %y store <2 x i64> %div, ptr addrspace(1) %out0 %rem = urem <2 x i64> %x, %y store <2 x i64> %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udiv_i8(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i8 %x, i8 %y) { ; GFX8-LABEL: udiv_i8: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_bfe_u32 s5, s4, 0x80008 ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, s5 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_sub_i32 s0, 0, s5 ; GFX8-NEXT: s_and_b32 s4, s4, 0xff ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s6, v0 ; GFX8-NEXT: s_mul_i32 s0, s0, s6 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s7, v0 ; GFX8-NEXT: s_add_i32 s6, s6, s7 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s5 ; GFX8-NEXT: s_sub_i32 s1, s4, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s6, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s5, s1 ; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udiv_i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_bfe_u32 s5, s4, 0x80008 ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_sub_i32 s6, 0, s5 ; GFX9-NEXT: s_and_b32 s4, s4, 0xff ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v0 ; GFX9-NEXT: s_mul_i32 s6, s6, s7 ; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6 ; GFX9-NEXT: s_add_i32 s7, s7, s6 ; GFX9-NEXT: s_mul_hi_u32 s6, s4, s7 ; GFX9-NEXT: s_mul_i32 s7, s6, s5 ; GFX9-NEXT: s_sub_i32 s4, s4, s7 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s8, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s8, s4 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s5, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: s_cselect_b32 s4, s5, s4 ; GFX9-NEXT: global_store_byte v1, v0, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: global_store_byte v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udiv_i8: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dword s0, s[8:9], 0x10 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_bfe_u32 s4, s0, 0x80008 ; GFX10-NEXT: s_and_b32 s0, s0, 0xff ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, s4 ; GFX10-NEXT: s_sub_i32 s2, 0, s4 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v0 ; GFX10-NEXT: s_mul_i32 s2, s2, s1 ; GFX10-NEXT: s_mul_hi_u32 s2, s1, s2 ; GFX10-NEXT: s_add_i32 s1, s1, s2 ; GFX10-NEXT: s_mul_hi_u32 s5, s0, s1 ; GFX10-NEXT: s_mul_i32 s1, s5, s4 ; GFX10-NEXT: s_sub_i32 s6, s0, s1 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s6, s4 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s5, s8, s5 ; GFX10-NEXT: s_sub_i32 s8, s6, s4 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_cmp_ge_u32 s6, s4 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s5, s8, s5 ; GFX10-NEXT: s_sub_i32 s4, s6, s4 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-NEXT: s_cselect_b32 s4, s4, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_byte v1, v0, s[0:1] ; GFX10-NEXT: global_store_byte v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv i8 %x, %y store i8 %div, ptr addrspace(1) %out0 %rem = urem i8 %x, %y store i8 %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_v2i8(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i8> %x, <2 x i8> %y) { ; GFX8-LABEL: udivrem_v2i8: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_bfe_u32 s0, s4, 0x80010 ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, s0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_sub_i32 s1, 0, s0 ; GFX8-NEXT: s_lshr_b32 s5, s4, 24 ; GFX8-NEXT: v_cvt_f32_ubyte3_e32 v1, s4 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: s_mul_i32 s1, s1, s2 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s1 ; GFX8-NEXT: s_and_b32 s1, s4, 0xff ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v0 ; GFX8-NEXT: s_add_i32 s2, s2, s3 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX8-NEXT: v_readfirstlane_b32 s6, v1 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: s_mul_i32 s3, s2, s0 ; GFX8-NEXT: s_sub_i32 s1, s1, s3 ; GFX8-NEXT: s_cmp_ge_u32 s1, s0 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 ; GFX8-NEXT: s_add_i32 s7, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0 ; GFX8-NEXT: s_cselect_b32 s2, s7, s2 ; GFX8-NEXT: s_sub_i32 s7, s1, s0 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0 ; GFX8-NEXT: s_cselect_b32 s1, s7, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s0 ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 ; GFX8-NEXT: s_add_i32 s7, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0 ; GFX8-NEXT: s_cselect_b32 s7, s7, s2 ; GFX8-NEXT: s_sub_i32 s0, s1, s0 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0 ; GFX8-NEXT: s_cselect_b32 s10, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, 0, s5 ; GFX8-NEXT: s_mul_i32 s0, s0, s6 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: s_bfe_u32 s4, s4, 0x80008 ; GFX8-NEXT: v_readfirstlane_b32 s8, v0 ; GFX8-NEXT: s_add_i32 s6, s6, s8 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s5 ; GFX8-NEXT: s_sub_i32 s1, s4, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s6, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s5, s1 ; GFX8-NEXT: s_and_b32 s0, s0, 0xff ; GFX8-NEXT: s_and_b32 s4, s7, 0xff ; GFX8-NEXT: s_lshl_b32 s0, s0, 8 ; GFX8-NEXT: s_or_b32 s0, s4, s0 ; GFX8-NEXT: s_and_b32 s1, s1, 0xff ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_and_b32 s0, s10, 0xff ; GFX8-NEXT: s_lshl_b32 s1, s1, 8 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_v2i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_bfe_u32 s5, s4, 0x80010 ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_sub_i32 s8, 0, s5 ; GFX9-NEXT: s_and_b32 s7, s4, 0xff ; GFX9-NEXT: s_lshr_b32 s6, s4, 24 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_ubyte3_e32 v1, s4 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s9, v0 ; GFX9-NEXT: s_mul_i32 s8, s8, s9 ; GFX9-NEXT: s_mul_hi_u32 s8, s9, s8 ; GFX9-NEXT: s_add_i32 s9, s9, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s7, s9 ; GFX9-NEXT: s_mul_i32 s9, s8, s5 ; GFX9-NEXT: s_sub_i32 s7, s7, s9 ; GFX9-NEXT: s_cmp_ge_u32 s7, s5 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s8, s10, s8 ; GFX9-NEXT: s_sub_i32 s10, s7, s5 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s7, s10, s7 ; GFX9-NEXT: s_cmp_ge_u32 s7, s5 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s8, 1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s8, s10, s8 ; GFX9-NEXT: s_sub_i32 s5, s7, s5 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s5, s5, s7 ; GFX9-NEXT: v_readfirstlane_b32 s7, v0 ; GFX9-NEXT: s_sub_i32 s9, 0, s6 ; GFX9-NEXT: s_mul_i32 s9, s9, s7 ; GFX9-NEXT: s_mul_hi_u32 s9, s7, s9 ; GFX9-NEXT: s_bfe_u32 s4, s4, 0x80008 ; GFX9-NEXT: s_add_i32 s7, s7, s9 ; GFX9-NEXT: s_mul_hi_u32 s7, s4, s7 ; GFX9-NEXT: s_mul_i32 s9, s7, s6 ; GFX9-NEXT: s_sub_i32 s4, s4, s9 ; GFX9-NEXT: s_cmp_ge_u32 s4, s6 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s7, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s7, s10, s7 ; GFX9-NEXT: s_sub_i32 s10, s4, s6 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s4, s10, s4 ; GFX9-NEXT: s_cmp_ge_u32 s4, s6 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s7, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s7, s10, s7 ; GFX9-NEXT: s_sub_i32 s6, s4, s6 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s4, s6, s4 ; GFX9-NEXT: s_and_b32 s7, s7, 0xff ; GFX9-NEXT: s_and_b32 s6, s8, 0xff ; GFX9-NEXT: s_lshl_b32 s7, s7, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_store_short v1, v0, s[0:1] ; GFX9-NEXT: s_and_b32 s1, s4, 0xff ; GFX9-NEXT: s_and_b32 s0, s5, 0xff ; GFX9-NEXT: s_lshl_b32 s1, s1, 8 ; GFX9-NEXT: s_or_b32 s0, s0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: global_store_short v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_v2i8: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dword s0, s[8:9], 0x10 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_bfe_u32 s1, s0, 0x80010 ; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v1, s0 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, s1 ; GFX10-NEXT: s_sub_i32 s3, 0, s1 ; GFX10-NEXT: s_and_b32 s4, s0, 0xff ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v1 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_mul_i32 s3, s3, s2 ; GFX10-NEXT: s_mul_hi_u32 s3, s2, s3 ; GFX10-NEXT: s_add_i32 s2, s2, s3 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: s_mul_hi_u32 s2, s4, s2 ; GFX10-NEXT: s_mul_i32 s3, s2, s1 ; GFX10-NEXT: s_sub_i32 s3, s4, s3 ; GFX10-NEXT: s_lshr_b32 s4, s0, 24 ; GFX10-NEXT: s_cmp_ge_u32 s3, s1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_add_i32 s6, s2, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s2, s6, s2 ; GFX10-NEXT: s_sub_i32 s6, s3, s1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s3, s6, s3 ; GFX10-NEXT: v_readfirstlane_b32 s6, v0 ; GFX10-NEXT: s_cmp_ge_u32 s3, s1 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_add_i32 s7, s2, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s7, s7, s2 ; GFX10-NEXT: s_sub_i32 s1, s3, s1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s5, s1, s3 ; GFX10-NEXT: s_sub_i32 s1, 0, s4 ; GFX10-NEXT: s_bfe_u32 s0, s0, 0x80008 ; GFX10-NEXT: s_mul_i32 s1, s1, s6 ; GFX10-NEXT: s_mul_hi_u32 s1, s6, s1 ; GFX10-NEXT: s_add_i32 s6, s6, s1 ; GFX10-NEXT: s_mul_hi_u32 s1, s0, s6 ; GFX10-NEXT: s_mul_i32 s2, s1, s4 ; GFX10-NEXT: s_sub_i32 s0, s0, s2 ; GFX10-NEXT: s_cmp_ge_u32 s0, s4 ; GFX10-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10-NEXT: s_add_i32 s3, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s6, s3, s1 ; GFX10-NEXT: s_sub_i32 s1, s0, s4 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s10, s1, s0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s10, s4 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s6, 1 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_sub_i32 s4, s10, s4 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cselect_b32 s4, s4, s10 ; GFX10-NEXT: s_and_b32 s6, s6, 0xff ; GFX10-NEXT: s_and_b32 s4, s4, 0xff ; GFX10-NEXT: s_and_b32 s7, s7, 0xff ; GFX10-NEXT: s_lshl_b32 s6, s6, 8 ; GFX10-NEXT: s_and_b32 s5, s5, 0xff ; GFX10-NEXT: s_lshl_b32 s4, s4, 8 ; GFX10-NEXT: s_or_b32 s6, s7, s6 ; GFX10-NEXT: s_or_b32 s4, s5, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_short v1, v0, s[0:1] ; GFX10-NEXT: global_store_short v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv <2 x i8> %x, %y store <2 x i8> %div, ptr addrspace(1) %out0 %rem = urem <2 x i8> %x, %y store <2 x i8> %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udiv_i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i16 %x, i16 %y) { ; GFX8-LABEL: udiv_i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_lshr_b32 s5, s4, 16 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX8-NEXT: s_sub_i32 s0, 0, s5 ; GFX8-NEXT: s_and_b32 s4, s4, 0xffff ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s6, v0 ; GFX8-NEXT: s_mul_i32 s0, s0, s6 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s7, v0 ; GFX8-NEXT: s_add_i32 s6, s6, s7 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s5 ; GFX8-NEXT: s_sub_i32 s1, s4, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s6, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s5, s1 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udiv_i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_lshr_b32 s5, s4, 16 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: s_sub_i32 s6, 0, s5 ; GFX9-NEXT: s_and_b32 s4, s4, 0xffff ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v0 ; GFX9-NEXT: s_mul_i32 s6, s6, s7 ; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6 ; GFX9-NEXT: s_add_i32 s7, s7, s6 ; GFX9-NEXT: s_mul_hi_u32 s6, s4, s7 ; GFX9-NEXT: s_mul_i32 s7, s6, s5 ; GFX9-NEXT: s_sub_i32 s4, s4, s7 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s8, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s8, s4 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s5, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: s_cselect_b32 s4, s5, s4 ; GFX9-NEXT: global_store_short v1, v0, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: global_store_short v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udiv_i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dword s0, s[8:9], 0x10 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_lshr_b32 s4, s0, 16 ; GFX10-NEXT: s_and_b32 s0, s0, 0xffff ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX10-NEXT: s_sub_i32 s2, 0, s4 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v0 ; GFX10-NEXT: s_mul_i32 s2, s2, s1 ; GFX10-NEXT: s_mul_hi_u32 s2, s1, s2 ; GFX10-NEXT: s_add_i32 s1, s1, s2 ; GFX10-NEXT: s_mul_hi_u32 s5, s0, s1 ; GFX10-NEXT: s_mul_i32 s1, s5, s4 ; GFX10-NEXT: s_sub_i32 s6, s0, s1 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s6, s4 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s5, s8, s5 ; GFX10-NEXT: s_sub_i32 s8, s6, s4 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_cmp_ge_u32 s6, s4 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s5, s8, s5 ; GFX10-NEXT: s_sub_i32 s4, s6, s4 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-NEXT: s_cselect_b32 s4, s4, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_short v1, v0, s[0:1] ; GFX10-NEXT: global_store_short v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv i16 %x, %y store i16 %div, ptr addrspace(1) %out0 %rem = urem i16 %x, %y store i16 %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_v2i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i16> %x, <2 x i16> %y) { ; GFX8-LABEL: udivrem_v2i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_and_b32 s2, s1, 0xffff ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX8-NEXT: s_lshr_b32 s4, s1, 16 ; GFX8-NEXT: s_sub_i32 s1, 0, s2 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s4 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v0 ; GFX8-NEXT: s_mul_i32 s1, s1, s3 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s1 ; GFX8-NEXT: s_and_b32 s1, s0, 0xffff ; GFX8-NEXT: v_readfirstlane_b32 s5, v0 ; GFX8-NEXT: s_add_i32 s3, s3, s5 ; GFX8-NEXT: v_mov_b32_e32 v0, s3 ; GFX8-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX8-NEXT: s_lshr_b32 s5, s0, 16 ; GFX8-NEXT: v_readfirstlane_b32 s0, v1 ; GFX8-NEXT: v_readfirstlane_b32 s3, v0 ; GFX8-NEXT: s_mul_i32 s6, s3, s2 ; GFX8-NEXT: s_sub_i32 s1, s1, s6 ; GFX8-NEXT: s_cmp_ge_u32 s1, s2 ; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: s_add_i32 s7, s3, 1 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_cselect_b32 s3, s7, s3 ; GFX8-NEXT: s_sub_i32 s7, s1, s2 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_cselect_b32 s1, s7, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s2 ; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: s_add_i32 s7, s3, 1 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_cselect_b32 s7, s7, s3 ; GFX8-NEXT: s_sub_i32 s2, s1, s2 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_cselect_b32 s6, s2, s1 ; GFX8-NEXT: s_sub_i32 s1, 0, s4 ; GFX8-NEXT: s_mul_i32 s1, s1, s0 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v0 ; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s8, v0 ; GFX8-NEXT: s_mul_i32 s9, s8, s4 ; GFX8-NEXT: s_sub_i32 s5, s5, s9 ; GFX8-NEXT: s_cmp_ge_u32 s5, s4 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s10, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: s_cselect_b32 s8, s10, s8 ; GFX8-NEXT: s_sub_i32 s10, s5, s4 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: s_cselect_b32 s5, s10, s5 ; GFX8-NEXT: s_cmp_ge_u32 s5, s4 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_add_i32 s10, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: s_cselect_b32 s8, s10, s8 ; GFX8-NEXT: s_sub_i32 s4, s5, s4 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_and_b32 s5, s7, 0xffff ; GFX8-NEXT: s_and_b32 s7, s8, 0xffff ; GFX8-NEXT: s_lshl_b32 s7, s7, 16 ; GFX8-NEXT: s_and_b32 s4, s4, 0xffff ; GFX8-NEXT: s_or_b32 s5, s5, s7 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: s_and_b32 s6, s6, 0xffff ; GFX8-NEXT: s_lshl_b32 s4, s4, 16 ; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: s_or_b32 s4, s6, s4 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_v2i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_and_b32 s6, s5, 0xffff ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX9-NEXT: s_sub_i32 s8, 0, s6 ; GFX9-NEXT: s_lshr_b32 s7, s4, 16 ; GFX9-NEXT: s_and_b32 s4, s4, 0xffff ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_lshr_b32 s5, s5, 16 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s9, v0 ; GFX9-NEXT: s_mul_i32 s8, s8, s9 ; GFX9-NEXT: s_mul_hi_u32 s8, s9, s8 ; GFX9-NEXT: s_add_i32 s9, s9, s8 ; GFX9-NEXT: s_mul_hi_u32 s8, s4, s9 ; GFX9-NEXT: s_mul_i32 s9, s8, s6 ; GFX9-NEXT: s_sub_i32 s4, s4, s9 ; GFX9-NEXT: s_cmp_ge_u32 s4, s6 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s8, s10, s8 ; GFX9-NEXT: s_sub_i32 s10, s4, s6 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s4, s10, s4 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 ; GFX9-NEXT: s_cmp_ge_u32 s4, s6 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s8, s10, s8 ; GFX9-NEXT: s_sub_i32 s6, s4, s6 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s4, s6, s4 ; GFX9-NEXT: v_readfirstlane_b32 s6, v1 ; GFX9-NEXT: s_sub_i32 s9, 0, s5 ; GFX9-NEXT: s_mul_i32 s9, s9, s6 ; GFX9-NEXT: s_mul_hi_u32 s9, s6, s9 ; GFX9-NEXT: s_add_i32 s6, s6, s9 ; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6 ; GFX9-NEXT: s_mul_i32 s9, s6, s5 ; GFX9-NEXT: s_sub_i32 s7, s7, s9 ; GFX9-NEXT: s_cmp_ge_u32 s7, s5 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s6, s10, s6 ; GFX9-NEXT: s_sub_i32 s10, s7, s5 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s7, s10, s7 ; GFX9-NEXT: s_cmp_ge_u32 s7, s5 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_add_i32 s10, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s6, s10, s6 ; GFX9-NEXT: s_sub_i32 s5, s7, s5 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_cselect_b32 s5, s5, s7 ; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s6 ; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_store_dword v1, v0, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: global_store_dword v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_v2i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x10 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_and_b32 s2, s1, 0xffff ; GFX10-NEXT: s_lshr_b32 s4, s1, 16 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GFX10-NEXT: s_sub_i32 s3, 0, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s4 ; GFX10-NEXT: s_and_b32 s5, s0, 0xffff ; GFX10-NEXT: s_lshr_b32 s0, s0, 16 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v1 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_mul_i32 s3, s3, s1 ; GFX10-NEXT: s_mul_hi_u32 s3, s1, s3 ; GFX10-NEXT: s_add_i32 s1, s1, s3 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: s_mul_hi_u32 s1, s5, s1 ; GFX10-NEXT: s_mul_i32 s3, s1, s2 ; GFX10-NEXT: s_sub_i32 s3, s5, s3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: s_cmp_ge_u32 s3, s2 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_add_i32 s6, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s1, s6, s1 ; GFX10-NEXT: s_sub_i32 s6, s3, s2 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s3, s6, s3 ; GFX10-NEXT: v_readfirstlane_b32 s6, v0 ; GFX10-NEXT: s_cmp_ge_u32 s3, s2 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_add_i32 s7, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s7, s7, s1 ; GFX10-NEXT: s_sub_i32 s1, s3, s2 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 ; GFX10-NEXT: s_cselect_b32 s5, s1, s3 ; GFX10-NEXT: s_sub_i32 s1, 0, s4 ; GFX10-NEXT: s_mul_i32 s1, s1, s6 ; GFX10-NEXT: s_mul_hi_u32 s1, s6, s1 ; GFX10-NEXT: s_add_i32 s6, s6, s1 ; GFX10-NEXT: s_mul_hi_u32 s1, s0, s6 ; GFX10-NEXT: s_mul_i32 s2, s1, s4 ; GFX10-NEXT: s_sub_i32 s0, s0, s2 ; GFX10-NEXT: s_cmp_ge_u32 s0, s4 ; GFX10-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10-NEXT: s_add_i32 s3, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s6, s3, s1 ; GFX10-NEXT: s_sub_i32 s1, s0, s4 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s10, s1, s0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s10, s4 ; GFX10-NEXT: s_cselect_b32 s8, 1, 0 ; GFX10-NEXT: s_add_i32 s9, s6, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_cselect_b32 s6, s9, s6 ; GFX10-NEXT: s_sub_i32 s4, s10, s4 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_pack_ll_b32_b16 s6, s7, s6 ; GFX10-NEXT: s_cselect_b32 s4, s4, s10 ; GFX10-NEXT: v_mov_b32_e32 v0, s6 ; GFX10-NEXT: s_pack_ll_b32_b16 s4, s5, s4 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv <2 x i16> %x, %y store <2 x i16> %div, ptr addrspace(1) %out0 %rem = urem <2 x i16> %x, %y store <2 x i16> %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_i3(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i3 %x, i3 %y) { ; GFX8-LABEL: udivrem_i3: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_bfe_u32 s5, s4, 0x30008 ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, s5 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_sub_i32 s0, 0, s5 ; GFX8-NEXT: s_and_b32 s4, s4, 7 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s6, v0 ; GFX8-NEXT: s_mul_i32 s0, s0, s6 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s7, v0 ; GFX8-NEXT: s_add_i32 s6, s6, s7 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s5 ; GFX8-NEXT: s_sub_i32 s1, s4, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s6, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s5, s1 ; GFX8-NEXT: s_and_b32 s0, s0, 7 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_and_b32 s0, s1, 7 ; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_i3: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s4, s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_bfe_u32 s5, s4, 0x30008 ; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_sub_i32 s6, 0, s5 ; GFX9-NEXT: s_and_b32 s4, s4, 7 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v0 ; GFX9-NEXT: s_mul_i32 s6, s6, s7 ; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6 ; GFX9-NEXT: s_add_i32 s7, s7, s6 ; GFX9-NEXT: s_mul_hi_u32 s6, s4, s7 ; GFX9-NEXT: s_mul_i32 s7, s6, s5 ; GFX9-NEXT: s_sub_i32 s4, s4, s7 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s8, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s8, s4 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s5, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s5, s4 ; GFX9-NEXT: s_and_b32 s5, s6, 7 ; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: s_and_b32 s4, s4, 7 ; GFX9-NEXT: global_store_byte v1, v0, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: global_store_byte v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_i3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dword s0, s[8:9], 0x10 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_bfe_u32 s4, s0, 0x30008 ; GFX10-NEXT: s_and_b32 s0, s0, 7 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, s4 ; GFX10-NEXT: s_sub_i32 s2, 0, s4 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v0 ; GFX10-NEXT: s_mul_i32 s2, s2, s1 ; GFX10-NEXT: s_mul_hi_u32 s2, s1, s2 ; GFX10-NEXT: s_add_i32 s1, s1, s2 ; GFX10-NEXT: s_mul_hi_u32 s1, s0, s1 ; GFX10-NEXT: s_mul_i32 s2, s1, s4 ; GFX10-NEXT: s_sub_i32 s0, s0, s2 ; GFX10-NEXT: s_cmp_ge_u32 s0, s4 ; GFX10-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10-NEXT: s_add_i32 s3, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s5, s3, s1 ; GFX10-NEXT: s_sub_i32 s1, s0, s4 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s6, s1, s0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s6, s4 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s5, s8, s5 ; GFX10-NEXT: s_sub_i32 s4, s6, s4 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s4, s4, s6 ; GFX10-NEXT: s_and_b32 s5, s5, 7 ; GFX10-NEXT: s_and_b32 s4, s4, 7 ; GFX10-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_byte v1, v0, s[0:1] ; GFX10-NEXT: global_store_byte v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv i3 %x, %y store i3 %div, ptr addrspace(1) %out0 %rem = urem i3 %x, %y store i3 %rem, ptr addrspace(1) %out1 ret void } define amdgpu_kernel void @udivrem_i27(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i27 %x, i27 %y) { ; GFX8-LABEL: udivrem_i27: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10 ; GFX8-NEXT: s_add_i32 s12, s12, s17 ; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_and_b32 s5, s5, 0x7ffffff ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX8-NEXT: s_sub_i32 s0, 0, s5 ; GFX8-NEXT: s_and_b32 s4, s4, 0x7ffffff ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s6, v0 ; GFX8-NEXT: s_mul_i32 s0, s0, s6 ; GFX8-NEXT: v_mul_hi_u32 v0, v0, s0 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX8-NEXT: v_readfirstlane_b32 s7, v0 ; GFX8-NEXT: s_add_i32 s6, s6, s7 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 ; GFX8-NEXT: s_mul_i32 s1, s0, s5 ; GFX8-NEXT: s_sub_i32 s1, s4, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s6, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_cmp_ge_u32 s1, s5 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0 ; GFX8-NEXT: s_add_i32 s6, s0, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s0, s6, s0 ; GFX8-NEXT: s_sub_i32 s5, s1, s5 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: s_cselect_b32 s1, s5, s1 ; GFX8-NEXT: s_and_b32 s0, s0, 0x7ffffff ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_and_b32 s0, s1, 0x7ffffff ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm ; ; GFX9-LABEL: udivrem_i27: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_and_b32 s5, s5, 0x7ffffff ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: s_sub_i32 s6, 0, s5 ; GFX9-NEXT: s_and_b32 s4, s4, 0x7ffffff ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v0 ; GFX9-NEXT: s_mul_i32 s6, s6, s7 ; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6 ; GFX9-NEXT: s_add_i32 s7, s7, s6 ; GFX9-NEXT: s_mul_hi_u32 s6, s4, s7 ; GFX9-NEXT: s_mul_i32 s7, s6, s5 ; GFX9-NEXT: s_sub_i32 s4, s4, s7 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s8, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s8, s4 ; GFX9-NEXT: s_cmp_ge_u32 s4, s5 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_sub_i32 s5, s4, s5 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cselect_b32 s4, s5, s4 ; GFX9-NEXT: s_and_b32 s5, s6, 0x7ffffff ; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: s_and_b32 s4, s4, 0x7ffffff ; GFX9-NEXT: global_store_dword v1, v0, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: global_store_dword v1, v0, s[2:3] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: udivrem_i27: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x10 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_and_b32 s4, s1, 0x7ffffff ; GFX10-NEXT: s_and_b32 s0, s0, 0x7ffffff ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX10-NEXT: s_sub_i32 s2, 0, s4 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v0 ; GFX10-NEXT: s_mul_i32 s2, s2, s1 ; GFX10-NEXT: s_mul_hi_u32 s2, s1, s2 ; GFX10-NEXT: s_add_i32 s1, s1, s2 ; GFX10-NEXT: s_mul_hi_u32 s1, s0, s1 ; GFX10-NEXT: s_mul_i32 s2, s1, s4 ; GFX10-NEXT: s_sub_i32 s0, s0, s2 ; GFX10-NEXT: s_cmp_ge_u32 s0, s4 ; GFX10-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10-NEXT: s_add_i32 s3, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s5, s3, s1 ; GFX10-NEXT: s_sub_i32 s1, s0, s4 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_cselect_b32 s6, s1, s0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; GFX10-NEXT: s_cmp_ge_u32 s6, s4 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_add_i32 s8, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s5, s8, s5 ; GFX10-NEXT: s_sub_i32 s4, s6, s4 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cselect_b32 s4, s4, s6 ; GFX10-NEXT: s_and_b32 s5, s5, 0x7ffffff ; GFX10-NEXT: s_and_b32 s4, s4, 0x7ffffff ; GFX10-NEXT: v_mov_b32_e32 v0, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[2:3] ; GFX10-NEXT: s_endpgm %div = udiv i27 %x, %y store i27 %div, ptr addrspace(1) %out0 %rem = urem i27 %x, %y store i27 %rem, ptr addrspace(1) %out1 ret void }