; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s

define amdgpu_kernel void @signal_unknown_wgs() {
; CHECK-LABEL: signal_unknown_wgs:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_barrier_signal -1
; CHECK-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
  ret void
}

define amdgpu_kernel void @signal_flat_wgs_attr_32_128() #1 {
; CHECK-LABEL: signal_flat_wgs_attr_32_128:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_barrier_signal -1
; CHECK-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
  ret void
}

define amdgpu_kernel void @signal_flat_wgs_attr_16_32() #2 {
; CHECK-LABEL: signal_flat_wgs_attr_16_32:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
  ret void
}


define amdgpu_kernel void @wait_unknown_wgs() {
; CHECK-LABEL: wait_unknown_wgs:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_barrier_wait -1
; CHECK-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
  ret void
}

define amdgpu_kernel void @wait_flat_wgs_attr_32_128() #1 {
; CHECK-LABEL: wait_flat_wgs_attr_32_128:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_barrier_wait -1
; CHECK-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
  ret void
}

define amdgpu_kernel void @wait_flat_wgs_attr_16_32() #2 {
; CHECK-LABEL: wait_flat_wgs_attr_16_32:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ; wave barrier
; CHECK-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
  ret void
}

declare void @llvm.amdgcn.s.barrier.signal(i32 immarg) #0
declare void @llvm.amdgcn.s.barrier.wait(i16 immarg) #0

attributes #0 = { convergent nounwind }
attributes #1 = { nounwind "amdgpu-flat-work-group-size"="32,128" }
attributes #2 = { nounwind "amdgpu-flat-work-group-size"="16,32" }