; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 %s -o - | FileCheck %s

define void @chain_node_divergence_update_crash(ptr addrspace(5) %ptr) {
; CHECK-LABEL: chain_node_divergence_update_crash:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_expcnt 0x0
; CHECK-NEXT:    s_wait_samplecnt 0x0
; CHECK-NEXT:    s_wait_bvhcnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    scratch_load_b32 v4, v0, off
; CHECK-NEXT:    s_mov_b32 s0, 0
; CHECK-NEXT:    s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT:    s_mov_b32 s1, s0
; CHECK-NEXT:    s_mov_b32 s2, s0
; CHECK-NEXT:    s_mov_b32 s3, s0
; CHECK-NEXT:    s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; CHECK-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; CHECK-NEXT:    s_wait_loadcnt 0x0
; CHECK-NEXT:    scratch_store_b128 v4, v[0:3], off
; CHECK-NEXT:    scratch_store_b128 off, v[0:3], s0
; CHECK-NEXT:    s_setpc_b64 s[30:31]
entry:
  %load = load ptr addrspace(5), ptr addrspace(5) %ptr, align 8
  store i64 0, ptr addrspace(5) %load, align 8
  %gep = getelementptr i8, ptr addrspace(5) %load, i32 8
  store i64 0, ptr addrspace(5) %gep, align 8
  call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) zeroinitializer, ptr addrspace(5) align 8 %load, i64 16, i1 false)
  ret void
}