# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx906 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s

# Make sure the modified CSR VGPRs are added as live-in to the entry
# block.

---
name: def_csr_sgpr
tracksRegLiveness: true
machineFunctionInfo:
  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
  stackPtrOffsetReg: $sgpr32
body: |
  ; CHECK-LABEL: name: def_csr_sgpr
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION undefined $sgpr42
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION undefined $sgpr43
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION undefined $sgpr46
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION undefined $sgpr47
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   $sgpr42 = S_MOV_B32 0
  ; CHECK-NEXT:   $sgpr43 = S_MOV_B32 1
  ; CHECK-NEXT:   $sgpr46_sgpr47 = S_MOV_B64 2
  bb.0:
    S_NOP 0

  bb.1:
    $sgpr42 = S_MOV_B32 0
    $sgpr43 = S_MOV_B32 1
    $sgpr46_sgpr47 = S_MOV_B64 2
...