; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX940 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s define void @s_add_use_fi_sgpr_offset(i32 inreg %soffset) #0 { ; GFX7-LABEL: s_add_use_fi_sgpr_offset: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_mov_b32 s7, s33 ; GFX7-NEXT: s_add_i32 s33, s32, 0x7c0 ; GFX7-NEXT: s_and_b32 s33, s33, 0xfffff800 ; GFX7-NEXT: s_mov_b32 s8, s34 ; GFX7-NEXT: s_mov_b32 s34, s32 ; GFX7-NEXT: s_add_i32 s32, s32, 0x45000 ; GFX7-NEXT: s_and_b32 s4, s16, 31 ; GFX7-NEXT: s_lshr_b32 s5, s33, 6 ; GFX7-NEXT: s_addk_i32 s5, 0x120 ; GFX7-NEXT: s_lshr_b32 s6, s33, 6 ; GFX7-NEXT: s_add_i32 s6, s6, 16 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use s5 ; GFX7-NEXT: ;;#ASMEND ; GFX7-NEXT: s_lshr_b32 s5, s33, 6 ; GFX7-NEXT: s_addk_i32 s5, 0x120 ; GFX7-NEXT: s_or_b32 s4, s4, s5 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use s4 ; GFX7-NEXT: ;;#ASMEND ; GFX7-NEXT: s_mov_b32 s32, s34 ; GFX7-NEXT: s_mov_b32 s34, s8 ; GFX7-NEXT: s_mov_b32 s33, s7 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: s_add_use_fi_sgpr_offset: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_mov_b32 s7, s33 ; GFX8-NEXT: s_add_i32 s33, s32, 0x7c0 ; GFX8-NEXT: s_and_b32 s33, s33, 0xfffff800 ; GFX8-NEXT: s_mov_b32 s8, s34 ; GFX8-NEXT: s_mov_b32 s34, s32 ; GFX8-NEXT: s_add_i32 s32, s32, 0x45000 ; GFX8-NEXT: s_and_b32 s4, s16, 31 ; GFX8-NEXT: s_lshr_b32 s5, s33, 6 ; GFX8-NEXT: s_addk_i32 s5, 0x120 ; GFX8-NEXT: s_lshr_b32 s6, s33, 6 ; GFX8-NEXT: s_add_i32 s6, s6, 16 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use s5 ; GFX8-NEXT: ;;#ASMEND ; GFX8-NEXT: s_lshr_b32 s5, s33, 6 ; GFX8-NEXT: s_addk_i32 s5, 0x120 ; GFX8-NEXT: s_or_b32 s4, s4, s5 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use s4 ; GFX8-NEXT: ;;#ASMEND ; GFX8-NEXT: s_mov_b32 s32, s34 ; GFX8-NEXT: s_mov_b32 s34, s8 ; GFX8-NEXT: s_mov_b32 s33, s7 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: s_add_use_fi_sgpr_offset: ; GFX900: ; %bb.0: ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_mov_b32 s7, s33 ; GFX900-NEXT: s_add_i32 s33, s32, 0x7c0 ; GFX900-NEXT: s_and_b32 s33, s33, 0xfffff800 ; GFX900-NEXT: s_mov_b32 s8, s34 ; GFX900-NEXT: s_mov_b32 s34, s32 ; GFX900-NEXT: s_add_i32 s32, s32, 0x45000 ; GFX900-NEXT: s_and_b32 s4, s16, 31 ; GFX900-NEXT: s_lshr_b32 s5, s33, 6 ; GFX900-NEXT: s_addk_i32 s5, 0x120 ; GFX900-NEXT: s_lshr_b32 s6, s33, 6 ; GFX900-NEXT: s_add_i32 s6, s6, 16 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s5 ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_lshr_b32 s5, s33, 6 ; GFX900-NEXT: s_addk_i32 s5, 0x120 ; GFX900-NEXT: s_or_b32 s4, s4, s5 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s4 ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s32, s34 ; GFX900-NEXT: s_mov_b32 s34, s8 ; GFX900-NEXT: s_mov_b32 s33, s7 ; GFX900-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: s_add_use_fi_sgpr_offset: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_mov_b32 s7, s33 ; GFX10-NEXT: s_add_i32 s33, s32, 0x3e0 ; GFX10-NEXT: s_mov_b32 s8, s34 ; GFX10-NEXT: s_and_b32 s33, s33, 0xfffffc00 ; GFX10-NEXT: s_mov_b32 s34, s32 ; GFX10-NEXT: s_add_i32 s32, s32, 0x22800 ; GFX10-NEXT: s_and_b32 s4, s16, 31 ; GFX10-NEXT: s_lshr_b32 s5, s33, 5 ; GFX10-NEXT: s_mov_b32 s32, s34 ; GFX10-NEXT: s_addk_i32 s5, 0x120 ; GFX10-NEXT: s_lshr_b32 s6, s33, 5 ; GFX10-NEXT: s_mov_b32 s34, s8 ; GFX10-NEXT: s_add_i32 s6, s6, 16 ; GFX10-NEXT: s_lshr_b32 s9, s33, 5 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s5 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: s_addk_i32 s9, 0x120 ; GFX10-NEXT: s_or_b32 s4, s4, s9 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s4 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: s_mov_b32 s33, s7 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: s_add_use_fi_sgpr_offset: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: s_mov_b32 s3, s33 ; GFX940-NEXT: s_add_i32 s33, s32, 31 ; GFX940-NEXT: s_andn2_b32 s33, s33, 31 ; GFX940-NEXT: s_mov_b32 s4, s34 ; GFX940-NEXT: s_mov_b32 s34, s32 ; GFX940-NEXT: s_addk_i32 s32, 0x1140 ; GFX940-NEXT: s_and_b32 s0, s0, 31 ; GFX940-NEXT: s_add_i32 s2, s33, 0x120 ; GFX940-NEXT: s_mov_b32 s1, s2 ; GFX940-NEXT: s_add_i32 s5, s33, 16 ; GFX940-NEXT: s_mov_b32 s2, s5 ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use s1 ; GFX940-NEXT: ;;#ASMEND ; GFX940-NEXT: s_add_i32 s1, s33, 0x120 ; GFX940-NEXT: s_or_b32 s0, s0, s1 ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use s0 ; GFX940-NEXT: ;;#ASMEND ; GFX940-NEXT: s_mov_b32 s32, s34 ; GFX940-NEXT: s_mov_b32 s34, s4 ; GFX940-NEXT: s_mov_b32 s33, s3 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: s_add_use_fi_sgpr_offset: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_mov_b32 s3, s33 ; GFX11-NEXT: s_add_i32 s33, s32, 31 ; GFX11-NEXT: s_mov_b32 s4, s34 ; GFX11-NEXT: s_and_not1_b32 s33, s33, 31 ; GFX11-NEXT: s_mov_b32 s34, s32 ; GFX11-NEXT: s_addk_i32 s32, 0x1140 ; GFX11-NEXT: s_and_b32 s0, s0, 31 ; GFX11-NEXT: s_add_i32 s2, s33, 0x120 ; GFX11-NEXT: s_add_i32 s5, s33, 16 ; GFX11-NEXT: s_mov_b32 s1, s2 ; GFX11-NEXT: s_mov_b32 s2, s5 ; GFX11-NEXT: s_add_i32 s5, s33, 0x120 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s1 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_or_b32 s0, s0, s5 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s0 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_mov_b32 s32, s34 ; GFX11-NEXT: s_mov_b32 s34, s4 ; GFX11-NEXT: s_mov_b32 s33, s3 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: s_add_use_fi_sgpr_offset: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX12-NEXT: s_wait_expcnt 0x0 ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: s_mov_b32 s3, s33 ; GFX12-NEXT: s_add_co_i32 s33, s32, 31 ; GFX12-NEXT: s_mov_b32 s4, s34 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_and_not1_b32 s33, s33, 31 ; GFX12-NEXT: s_mov_b32 s34, s32 ; GFX12-NEXT: s_addk_co_i32 s32, 0x1140 ; GFX12-NEXT: s_and_b32 s0, s0, 31 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_add_co_i32 s2, s33, 0x100 ; GFX12-NEXT: s_add_co_i32 s5, s33, 0x100 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_mov_b32 s1, s2 ; GFX12-NEXT: s_mov_b32 s2, s33 ; GFX12-NEXT: s_or_b32 s0, s0, s5 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s1 ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s0 ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: s_mov_b32 s32, s34 ; GFX12-NEXT: s_mov_b32 s34, s4 ; GFX12-NEXT: s_mov_b32 s33, s3 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[30:31] %filler = alloca [256 x i8], align 16, addrspace(5) %alloca = alloca [4096 x i8], align 32, addrspace(5) %soffset.and = and i32 %soffset, 31 call void asm sideeffect "; use $0", "s,s"(ptr addrspace(5) %alloca, ptr addrspace(5) %filler) %gep = getelementptr inbounds nuw [4096 x i8], ptr addrspace(5) %alloca, i32 0, i32 %soffset.and call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %gep) ret void }