# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s

# Test handling of the GFX1250 hardware hazard where S_SET_VGPR_MSB immediately
# after S_SETREG_IMM32_B32 (MODE) is silently dropped.
#
# AMDGPULowerVGPREncoding may place S_SET_VGPR_MSB after S_SETREG_IMM32_B32
# (MODE) in Case 2 (size > 12). It inserts S_NOPs between them to prevent
# the hazard.

---
# Case 2 mismatch: setreg (size=16) with imm32[12:19] that doesn't match
# current VGPR MSB. AMDGPULowerVGPREncoding inserts S_NOP + S_SET_VGPR_MSB
# after the setreg.
name: setreg_mode_size_gt_12_mismatch
tracksRegLiveness: true
body: |
  bb.0:
    ; CHECK-LABEL: name: setreg_mode_size_gt_12_mismatch
    ; CHECK: S_SET_VGPR_MSB 64, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 6844, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16384, implicit-def $mode
    ; CHECK-NEXT: SI_RETURN
    $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
    ; imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23, doesn't match VGPR MSB mode)
    S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
    SI_RETURN
...

---
# Case 2 with different next MSB: setreg (size=16) with imm32[12:19] that
# doesn't match current VGPR MSB. S_NOP + S_SET_VGPR_MSB are inserted for the
# next VALU (v512/v513).
name: setreg_mode_size_gt_12_matches_next
tracksRegLiveness: true
body: |
  bb.0:
    ; CHECK-LABEL: name: setreg_mode_size_gt_12_matches_next
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16770, implicit-def $mode
    ; CHECK-NEXT: $vgpr512 = V_MOV_B32_e32 undef $vgpr513, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 undef $vgpr257, implicit $exec
    ; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
    ; imm32 = 0xAABC = 43708 (bits 12:19 = 0xA = 10, matches next MSB for v512/v513)
    S_SETREG_IMM32_B32 43708, 30721, implicit-def $mode, implicit $mode
    $vgpr512 = V_MOV_B32_e32 undef $vgpr513, implicit $exec
    S_ENDPGM 0
...

---
# No hazard: S_SETREG_IMM32_B32 targeting non-MODE register.
name: setreg_non_mode_no_hazard
tracksRegLiveness: true
body: |
  bb.0:
    ; CHECK-LABEL: name: setreg_non_mode_no_hazard
    ; CHECK: S_SET_VGPR_MSB 64, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 0, 2178, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_SET_VGPR_MSB 16384, implicit-def $mode
    ; CHECK-NEXT: $vgpr0 = V_ADD_F32_e32 undef $vgpr1, undef $vgpr2, implicit $exec, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; hwreg(STATUS, 2, 2): simm16 = 2 | (2 << 6) | (1 << 11) = 0x882 = 2178
    S_SETREG_IMM32_B32 0, 2178, implicit-def $mode, implicit $mode
    $vgpr0 = V_ADD_F32_e32 undef $vgpr1, undef $vgpr2, implicit $exec, implicit $mode
    S_ENDPGM 0
...

---
# Case 2 but no high VGPRs before setreg.
name: setreg_mode_size_gt_12_no_high_vgpr
tracksRegLiveness: true
body: |
  bb.0:
    ; CHECK-LABEL: name: setreg_mode_size_gt_12_no_high_vgpr
    ; CHECK: $vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 2748, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: SI_RETURN
    $vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
    S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
    SI_RETURN
...

---
# Case 2 with high VGPR only AFTER setreg: setreg (size=16) with low VGPRs
# before but high VGPRs after. AMDGPULowerVGPREncoding inserts S_NOP +
# S_SET_VGPR_MSB before the next VALU (which is right after setreg).
name: setreg_mode_size_gt_12_high_vgpr_after
tracksRegLiveness: true
body: |
  bb.0:
    ; CHECK-LABEL: name: setreg_mode_size_gt_12_high_vgpr_after
    ; CHECK: $vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 2748, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 64, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    ; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
    S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
    $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
    S_ENDPGM 0
...